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| author | Chia-I Wu <olv@lunarg.com> | 2010-12-04 21:02:50 +0800 |
|---|---|---|
| committer | Chia-I Wu <olv@lunarg.com> | 2010-12-04 23:41:30 +0800 |
| commit | 5d244111404fc36c55266f9703f81b27a5200a47 (patch) | |
| tree | fa4353a00ce3162feb8488ff1533ad72372b214f | |
| parent | 09fba30fded4505e2cc5a93fd84cb1a73b7320a7 (diff) | |
st/vega: Fix VG_BLEND_MULTIPLY.
TEMP[1].w will be needed for OUT.w just below. Use TEMP[0] to store the
intermediate value.
| -rw-r--r-- | src/gallium/state_trackers/vega/asm_fill.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/state_trackers/vega/asm_fill.h b/src/gallium/state_trackers/vega/asm_fill.h index 566f7c95f5..5ff76975e2 100644 --- a/src/gallium/state_trackers/vega/asm_fill.h +++ b/src/gallium/state_trackers/vega/asm_fill.h @@ -367,7 +367,7 @@ blend_generic(struct ureg_program *ureg, ureg_scalar(dst, TGSI_SWIZZLE_W), ureg_negate(src), src); ureg_MAD(ureg, temp[1], src_channel_alpha, ureg_negate(dst), dst); - ureg_MAD(ureg, temp[1], src, dst, ureg_src(temp[1])); + ureg_MAD(ureg, temp[0], src, dst, ureg_src(temp[0])); ureg_ADD(ureg, out, ureg_src(temp[0]), ureg_src(temp[1])); /* alpha is src over */ ureg_ADD(ureg, ureg_writemask(out, TGSI_WRITEMASK_W), |