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authorMichal Krol <michal@vmware.com>2009-07-30 11:39:06 +0200
committerMichal Krol <michal@vmware.com>2009-07-30 11:39:06 +0200
commit6c70285e330bd19db78b7d45e43a01b0255ca15f (patch)
tree35345dabf208c76a486756f2165c208aee6b4b2d
parentcf8907018e449580b397f09c267219a612ba5db4 (diff)
tgsi: Add proper constraints to sanity.
-rw-r--r--src/gallium/auxiliary/tgsi/tgsi_sanity.c24
1 files changed, 22 insertions, 2 deletions
diff --git a/src/gallium/auxiliary/tgsi/tgsi_sanity.c b/src/gallium/auxiliary/tgsi/tgsi_sanity.c
index 8bb186bae5..cb62a95fc0 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_sanity.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_sanity.c
@@ -235,9 +235,29 @@ iter_instruction(
index,
"indirect",
FALSE );
- if (file != TGSI_FILE_ADDRESS || index != 0)
- report_warning( ctx, "Indirect register not ADDR[0]" );
+ if (!(file == TGSI_FILE_ADDRESS || file == TGSI_FILE_LOOP) || index != 0) {
+ report_warning(ctx, "Indirect register neither ADDR[0] nor LOOP[0]");
+ }
+ }
+ }
+
+ switch (inst->Instruction.Opcode) {
+ case TGSI_OPCODE_LOOP:
+ case TGSI_OPCODE_ENDLOOP:
+ if (inst->FullDstRegisters[0].DstRegister.File != TGSI_FILE_LOOP ||
+ inst->FullDstRegisters[0].DstRegister.Index != 0) {
+ report_error(ctx, "Destination register must be LOOP[0]");
+ }
+ break;
+ }
+
+ switch (inst->Instruction.Opcode) {
+ case TGSI_OPCODE_LOOP:
+ if (inst->FullSrcRegisters[0].SrcRegister.File != TGSI_FILE_CONSTANT &&
+ inst->FullSrcRegisters[0].SrcRegister.File != TGSI_FILE_IMMEDIATE) {
+ report_error(ctx, "Source register file must be either CONST or IMM");
}
+ break;
}
ctx->num_instructions++;