summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorZou Nan hai <nanhai.zou@intel.com>2010-05-18 16:22:40 +0800
committerEric Anholt <eric@anholt.net>2010-05-28 12:51:48 -0700
commit9390af0d9636ed8e985ff22cdbbbf9b12c3a7586 (patch)
treea352a46ad7392f74eeb5a9f0cbf601d1ccc9e167
parente6d8b4090f72f96485ee1589c114d9cf1e6f9db4 (diff)
i965: fix PIPE_CONTROL command for gen6.
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
-rw-r--r--src/mesa/drivers/dri/intel/intel_batchbuffer.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index de5134008f..446ce29984 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -275,7 +275,16 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
{
struct intel_context *intel = batch->intel;
- if (intel->gen >= 4) {
+ if (intel->gen >= 6) {
+ BEGIN_BATCH(4);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
+ PIPE_CONTROL_WRITE_FLUSH |
+ PIPE_CONTROL_NO_WRITE);
+ OUT_BATCH(0); /* write address */
+ OUT_BATCH(0); /* write data */
+ ADVANCE_BATCH();
+ } else if (intel->gen >= 4) {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL |
PIPE_CONTROL_WRITE_FLUSH |