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| author | Jonathan White <jwhite@tungstengraphics.com> | 2008-09-22 14:33:53 -0600 |
|---|---|---|
| committer | Jonathan White <jwhite@tungstengraphics.com> | 2008-09-22 14:33:53 -0600 |
| commit | 6642380841b8cc0d166bf1c6a76be786e1c50825 (patch) | |
| tree | 42da91bf954af1f5ee7d21d548b67d87254eea12 | |
| parent | 6b3ec9ec2b96e33f975852ee9f4751c6fefe9869 (diff) | |
cell: Fixed bug with absolute, negate, set-negative logic in source fetch for TGSI instructions. The logic should operate on the origin channel not the swizzled channel.
Please enter the commit message for your changes.
| -rw-r--r-- | src/gallium/drivers/cell/ppu/cell_gen_fp.c | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/src/gallium/drivers/cell/ppu/cell_gen_fp.c b/src/gallium/drivers/cell/ppu/cell_gen_fp.c index 4b8189207d..8972b5b1ea 100644 --- a/src/gallium/drivers/cell/ppu/cell_gen_fp.c +++ b/src/gallium/drivers/cell/ppu/cell_gen_fp.c @@ -184,31 +184,27 @@ get_src_reg(struct codegen *gen, assert(swizzle >= TGSI_SWIZZLE_X); assert(swizzle <= TGSI_EXTSWIZZLE_ONE); - channel = swizzle; - switch (src->SrcRegister.File) { case TGSI_FILE_TEMPORARY: - reg = gen->temp_regs[src->SrcRegister.Index][channel]; + reg = gen->temp_regs[src->SrcRegister.Index][swizzle]; break; case TGSI_FILE_INPUT: { - if(channel == TGSI_EXTSWIZZLE_ONE) + if(swizzle == TGSI_EXTSWIZZLE_ONE) { /* Load const one float and early out */ reg = get_const_one_reg(gen); - return reg; } - else if(channel == TGSI_EXTSWIZZLE_ZERO) + else if(swizzle == TGSI_EXTSWIZZLE_ZERO) { /* Load const zero float and early out */ reg = get_itemp(gen); spe_xor(gen->f, reg, reg, reg); - return reg; } else { /* offset is measured in quadwords, not bytes */ - int offset = src->SrcRegister.Index * 4 + channel; + int offset = src->SrcRegister.Index * 4 + swizzle; reg = get_itemp(gen); reg_is_itemp = TRUE; /* Load: reg = memory[(machine_reg) + offset] */ @@ -217,7 +213,7 @@ get_src_reg(struct codegen *gen, } break; case TGSI_FILE_IMMEDIATE: - reg = gen->imm_regs[src->SrcRegister.Index][channel]; + reg = gen->imm_regs[src->SrcRegister.Index][swizzle]; break; case TGSI_FILE_CONSTANT: /* xxx fall-through for now / fix */ |