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authorEric Anholt <eric@anholt.net>2010-03-16 12:59:59 -0700
committerEric Anholt <eric@anholt.net>2010-03-16 13:18:54 -0700
commit800a4b202f8b23540dbb128e780ca8b7e90d1f46 (patch)
tree82ddc4e276fab337a5becc1275715abf79e6e7b5
parent25becb8a7a40741afd6df445e6f96433fcb91b36 (diff)
intel: Remove more code for x8z24 visuals, since we only do s8z24.
-rw-r--r--src/mesa/drivers/dri/intel/intel_screen.c19
1 files changed, 7 insertions, 12 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 6e4bb64365..5e3f40836d 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -312,18 +312,13 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
}
if (mesaVis->depthBits == 24) {
- if (mesaVis->stencilBits == 8) {
- /* combined depth/stencil buffer */
- struct intel_renderbuffer *depthStencilRb
- = intel_create_renderbuffer(MESA_FORMAT_S8_Z24);
- /* note: bind RB to two attachment points */
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthStencilRb->Base);
- _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &depthStencilRb->Base);
- } else {
- struct intel_renderbuffer *depthRb
- = intel_create_renderbuffer(MESA_FORMAT_X8_Z24);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
- }
+ assert(mesaVis->stencilBits == 8);
+ /* combined depth/stencil buffer */
+ struct intel_renderbuffer *depthStencilRb
+ = intel_create_renderbuffer(MESA_FORMAT_S8_Z24);
+ /* note: bind RB to two attachment points */
+ _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthStencilRb->Base);
+ _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &depthStencilRb->Base);
}
else if (mesaVis->depthBits == 16) {
/* just 16-bit depth buffer, no hw stencil */