diff options
| author | Jerome Glisse <jglisse@redhat.com> | 2010-08-03 15:49:21 -0400 |
|---|---|---|
| committer | Jerome Glisse <jglisse@redhat.com> | 2010-08-03 15:49:21 -0400 |
| commit | 8f6341d42131e6f60f269610d62b7f5b7b683052 (patch) | |
| tree | 321202d6a245fed3bec070df69303bad560a104e | |
| parent | 7e42b7e5d2aebcda0e6bf081b6661411731e6df2 (diff) | |
r600g: fix stencil
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
| -rw-r--r-- | src/gallium/drivers/r600/r600_blit.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_state.c | 13 |
2 files changed, 7 insertions, 8 deletions
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c index cc37227ead..f4eedfe4cb 100644 --- a/src/gallium/drivers/r600/r600_blit.c +++ b/src/gallium/drivers/r600/r600_blit.c @@ -86,7 +86,6 @@ static void r600_clear_render_target(struct pipe_context *pipe, util_blitter_clear_render_target(rctx->blitter, dst, rgba, dstx, dsty, width, height); -R600_ERR("vtx elem %p\n", rctx->vertex_elements); } static void r600_clear_depth_stencil(struct pipe_context *pipe, @@ -105,7 +104,6 @@ static void r600_clear_depth_stencil(struct pipe_context *pipe, util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil, dstx, dsty, width, height); -R600_ERR("vtx elem %p\n", rctx->vertex_elements); } static void r600_resource_copy_region(struct pipe_context *pipe, diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 60270e18a6..f687d31e4b 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -869,6 +869,7 @@ static struct radeon_state *r600_viewport(struct r600_context *rctx) static struct radeon_state *r600_dsa(struct r600_context *rctx) { const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa; + const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref; struct r600_screen *rscreen = rctx->screen; struct radeon_state *rstate; unsigned db_depth_control, alpha_test_control, alpha_ref; @@ -880,30 +881,30 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx) stencil_ref_mask = 0; stencil_ref_mask_bf = 0; - db_depth_control = 0x00700700 | - S_028800_Z_ENABLE(state->depth.enabled) | + db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func); /* set stencil enable */ - db_depth_control |= S_028800_STENCIL_ENABLE(state->stencil[0].enabled); - - if (state->stencil[0].enabled) { + if (state->stencil[0].enabled) { + db_depth_control |= S_028800_STENCIL_ENABLE(1); db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func)); db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); - db_depth_control |= S_028800_BACKFACE_ENABLE(state->stencil[1].enabled); stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) | S_028430_STENCILWRITEMASK(state->stencil[0].writemask); + stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]); if (state->stencil[1].enabled) { + db_depth_control |= S_028800_BACKFACE_ENABLE(1); db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func)); db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) | S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask); + stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]); } } |