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authorXiang, Haihao <haihao.xiang@intel.com>2008-10-13 13:04:04 +0800
committerXiang, Haihao <haihao.xiang@intel.com>2008-10-13 13:04:04 +0800
commitc238098bbcfb644ea01b33d3274b949d84822512 (patch)
treea326447c7bcb44be0341a1da0d3c681828392fb8
parent5c39bad220c801490ac3d99af01d4c4a7e05dfd6 (diff)
i915: Texture instructions use r/t/oC/oD register as texture coordinate.
Fix http://bugs.freedesktop.org/show_bug.cgi?id=16287.
-rw-r--r--src/mesa/drivers/dri/i915/i915_program.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i915/i915_program.c b/src/mesa/drivers/dri/i915/i915_program.c
index 350da5e169..e87700f8e0 100644
--- a/src/mesa/drivers/dri/i915/i915_program.c
+++ b/src/mesa/drivers/dri/i915/i915_program.c
@@ -245,6 +245,19 @@ GLuint i915_emit_texld( struct i915_fragment_program *p,
*/
assert(GET_UREG_TYPE(coord) != REG_TYPE_U);
+ if ((GET_UREG_TYPE(coord) != REG_TYPE_R) &&
+ (GET_UREG_TYPE(coord) != REG_TYPE_OC) &&
+ (GET_UREG_TYPE(coord) != REG_TYPE_OD) &&
+ (GET_UREG_TYPE(coord) != REG_TYPE_T)) {
+ GLuint tmpCoord = get_free_rreg(p, live_regs);
+
+ if (tmpCoord == UREG_BAD)
+ return 0;
+
+ i915_emit_arith(p, A0_MOV, tmpCoord, A0_DEST_CHANNEL_ALL, 0, coord, 0, 0);
+ coord = tmpCoord;
+ }
+
/* Output register being oC or oD defines a phase boundary */
if (GET_UREG_TYPE(dest) == REG_TYPE_OC ||
GET_UREG_TYPE(dest) == REG_TYPE_OD)