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authorBrian Paul <brian.paul@tungstengraphics.com>2008-10-07 16:11:20 -0600
committerBrian Paul <brian.paul@tungstengraphics.com>2008-10-07 16:16:27 -0600
commitce416566bc71d2463785a834ffbe14fb5e9eae03 (patch)
treeb2af319a9f403bd3b728ff6cdb0b23c8a1207eb8
parent3008657ceaec3f91386c767c51647729afe16b34 (diff)
cell: fix incorrect extended swizzle term code in get_src_reg()
-rw-r--r--src/gallium/drivers/cell/ppu/cell_gen_fp.c50
1 files changed, 26 insertions, 24 deletions
diff --git a/src/gallium/drivers/cell/ppu/cell_gen_fp.c b/src/gallium/drivers/cell/ppu/cell_gen_fp.c
index 5d16fc13fe..131a2356fe 100644
--- a/src/gallium/drivers/cell/ppu/cell_gen_fp.c
+++ b/src/gallium/drivers/cell/ppu/cell_gen_fp.c
@@ -185,22 +185,24 @@ get_src_reg(struct codegen *gen,
assert(swizzle >= TGSI_SWIZZLE_X);
assert(swizzle <= TGSI_EXTSWIZZLE_ONE);
- switch (src->SrcRegister.File) {
- case TGSI_FILE_TEMPORARY:
- reg = gen->temp_regs[src->SrcRegister.Index][swizzle];
- break;
- case TGSI_FILE_INPUT:
- {
- if (swizzle == TGSI_EXTSWIZZLE_ONE) {
- /* Load const one float and early out */
- reg = get_const_one_reg(gen);
- }
- else if (swizzle == TGSI_EXTSWIZZLE_ZERO) {
- /* Load const zero float and early out */
- reg = get_itemp(gen);
- spe_xor(gen->f, reg, reg, reg);
- }
- else {
+ if (swizzle == TGSI_EXTSWIZZLE_ONE) {
+ /* Load const one float and early out */
+ reg = get_const_one_reg(gen);
+ }
+ else if (swizzle == TGSI_EXTSWIZZLE_ZERO) {
+ /* Load const zero float and early out */
+ reg = get_itemp(gen);
+ spe_xor(gen->f, reg, reg, reg);
+ }
+ else {
+ assert(swizzle < 4);
+
+ switch (src->SrcRegister.File) {
+ case TGSI_FILE_TEMPORARY:
+ reg = gen->temp_regs[src->SrcRegister.Index][swizzle];
+ break;
+ case TGSI_FILE_INPUT:
+ {
/* offset is measured in quadwords, not bytes */
int offset = src->SrcRegister.Index * 4 + swizzle;
reg = get_itemp(gen);
@@ -208,15 +210,15 @@ get_src_reg(struct codegen *gen,
/* Load: reg = memory[(machine_reg) + offset] */
spe_lqd(gen->f, reg, gen->inputs_reg, offset);
}
+ break;
+ case TGSI_FILE_IMMEDIATE:
+ reg = gen->imm_regs[src->SrcRegister.Index][swizzle];
+ break;
+ case TGSI_FILE_CONSTANT:
+ /* xxx fall-through for now / fix */
+ default:
+ assert(0);
}
- break;
- case TGSI_FILE_IMMEDIATE:
- reg = gen->imm_regs[src->SrcRegister.Index][swizzle];
- break;
- case TGSI_FILE_CONSTANT:
- /* xxx fall-through for now / fix */
- default:
- assert(0);
}
/*