nouveau: s/rankine/eng3d/g; s/curie/eng3d/g

Result of running:
perl -i -p -e 's/rankine/eng3d/g; s/curie/eng3d/g;' nv[34]0/*.[ch]

This will allow to more easily unify nv30 and nv40.

32 files changed, 289 insertions, 289 deletions

diff --git a/src/gallium/drivers/nv30/nv30_context.c b/src/gallium/drivers/nv30/nv30_context.c
index 825c167b01..be6407805b 100644
--- a/src/gallium/drivers/nv30/nv30_context.c
+++ b/src/gallium/drivers/nv30/nv30_context.c
@@ -11,12 +11,12 @@ nv30_flush(struct pipe_context *pipe, unsigned flags,
 	struct nv30_context *nv30 = nv30_context(pipe);
 	struct nv30_screen *screen = nv30->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *rankine = screen->rankine;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 
 	if (flags & PIPE_FLUSH_TEXTURE_CACHE) {
-		BEGIN_RING(chan, rankine, 0x1fd8, 1);
+		BEGIN_RING(chan, eng3d, 0x1fd8, 1);
 		OUT_RING  (chan, 2);
-		BEGIN_RING(chan, rankine, 0x1fd8, 1);
+		BEGIN_RING(chan, eng3d, 0x1fd8, 1);
 		OUT_RING  (chan, 1);
 	}
 
diff --git a/src/gallium/drivers/nv30/nv30_fragprog.c b/src/gallium/drivers/nv30/nv30_fragprog.c
index 74bf68012a..4c96e6d733 100644
--- a/src/gallium/drivers/nv30/nv30_fragprog.c
+++ b/src/gallium/drivers/nv30/nv30_fragprog.c
@@ -836,16 +836,16 @@ nv30_fragprog_validate(struct nv30_context *nv30)
 	nv30_fragprog_upload(nv30, fp);
 
 	so = so_new(4, 4, 1);
-	so_method(so, nv30->screen->rankine, NV34TCL_FP_ACTIVE_PROGRAM, 1);
+	so_method(so, nv30->screen->eng3d, NV34TCL_FP_ACTIVE_PROGRAM, 1);
 	so_reloc (so, nouveau_bo(fp->buffer), 0, NOUVEAU_BO_VRAM |
 		      NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
 		      NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
 		      NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
-	so_method(so, nv30->screen->rankine, NV34TCL_FP_CONTROL, 1);
+	so_method(so, nv30->screen->eng3d, NV34TCL_FP_CONTROL, 1);
 	so_data  (so, fp->fp_control);
-	so_method(so, nv30->screen->rankine, NV34TCL_FP_REG_CONTROL, 1);
+	so_method(so, nv30->screen->eng3d, NV34TCL_FP_REG_CONTROL, 1);
 	so_data  (so, (1<<16)|0x4);
-	so_method(so, nv30->screen->rankine, NV34TCL_TX_UNITS_ENABLE, 1);
+	so_method(so, nv30->screen->eng3d, NV34TCL_TX_UNITS_ENABLE, 1);
 	so_data  (so, fp->samplers);
 	so_ref(so, &fp->so);
 	so_ref(NULL, &so);
diff --git a/src/gallium/drivers/nv30/nv30_fragtex.c b/src/gallium/drivers/nv30/nv30_fragtex.c
index f7d98f3f20..63b5015ed4 100644
--- a/src/gallium/drivers/nv30/nv30_fragtex.c
+++ b/src/gallium/drivers/nv30/nv30_fragtex.c
@@ -101,7 +101,7 @@ nv30_fragtex_build(struct nv30_context *nv30, int unit)
 	txs = tf->swizzle;
 
 	so = so_new(1, 8, 2);
-	so_method(so, nv30->screen->rankine, NV34TCL_TX_OFFSET(unit), 8);
+	so_method(so, nv30->screen->eng3d, NV34TCL_TX_OFFSET(unit), 8);
 	so_reloc (so, bo, 0, tex_flags | NOUVEAU_BO_LOW, 0, 0);
 	so_reloc (so, bo, txf, tex_flags | NOUVEAU_BO_OR,
 		      NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1);
@@ -130,7 +130,7 @@ nv30_fragtex_validate(struct nv30_context *nv30)
 		samplers &= ~(1 << unit);
 
 		so = so_new(1, 1, 0);
-		so_method(so, nv30->screen->rankine, NV34TCL_TX_ENABLE(unit), 1);
+		so_method(so, nv30->screen->eng3d, NV34TCL_TX_ENABLE(unit), 1);
 		so_data  (so, 0);
 		so_ref(so, &nv30->state.hw[NV30_STATE_FRAGTEX0 + unit]);
 		so_ref(NULL, &so);
diff --git a/src/gallium/drivers/nv30/nv30_query.c b/src/gallium/drivers/nv30/nv30_query.c
index e27e9ccbf6..21a5e8ad7c 100644
--- a/src/gallium/drivers/nv30/nv30_query.c
+++ b/src/gallium/drivers/nv30/nv30_query.c
@@ -43,7 +43,7 @@ nv30_query_begin(struct pipe_context *pipe, struct pipe_query *pq)
 	struct nv30_query *q = nv30_query(pq);
 	struct nv30_screen *screen = nv30->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *rankine = screen->rankine;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 
 	assert(q->type == PIPE_QUERY_OCCLUSION_COUNTER);
 
@@ -60,9 +60,9 @@ nv30_query_begin(struct pipe_context *pipe, struct pipe_query *pq)
 		assert(0);
 	nouveau_notifier_reset(nv30->screen->query, q->object->start);
 
-	BEGIN_RING(chan, rankine, NV34TCL_QUERY_RESET, 1);
+	BEGIN_RING(chan, eng3d, NV34TCL_QUERY_RESET, 1);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, rankine, NV34TCL_QUERY_UNK17CC, 1);
+	BEGIN_RING(chan, eng3d, NV34TCL_QUERY_UNK17CC, 1);
 	OUT_RING  (chan, 1);
 
 	q->ready = FALSE;
@@ -74,10 +74,10 @@ nv30_query_end(struct pipe_context *pipe, struct pipe_query *pq)
 	struct nv30_context *nv30 = nv30_context(pipe);
 	struct nv30_screen *screen = nv30->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *rankine = screen->rankine;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 	struct nv30_query *q = nv30_query(pq);
 
-	BEGIN_RING(chan, rankine, NV34TCL_QUERY_GET, 1);
+	BEGIN_RING(chan, eng3d, NV34TCL_QUERY_GET, 1);
 	OUT_RING  (chan, (0x01 << NV34TCL_QUERY_GET_UNK24_SHIFT) |
 		   ((q->object->start * 32) << NV34TCL_QUERY_GET_OFFSET_SHIFT));
 	FIRE_RING(chan);
diff --git a/src/gallium/drivers/nv30/nv30_screen.c b/src/gallium/drivers/nv30/nv30_screen.c
index db24335b7c..40193f2795 100644
--- a/src/gallium/drivers/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nv30/nv30_screen.c
@@ -177,7 +177,7 @@ nv30_screen_destroy(struct pipe_screen *pscreen)
 	nouveau_resource_destroy(&screen->query_heap);
 	nouveau_notifier_free(&screen->query);
 	nouveau_notifier_free(&screen->sync);
-	nouveau_grobj_free(&screen->rankine);
+	nouveau_grobj_free(&screen->eng3d);
 	nv04_surface_2d_takedown(&screen->eng2d);
 
 	nouveau_screen_fini(&screen->base);
@@ -192,7 +192,7 @@ nv30_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 	struct nouveau_channel *chan;
 	struct pipe_screen *pscreen;
 	struct nouveau_stateobj *so;
-	unsigned rankine_class = 0;
+	unsigned eng3d_class = 0;
 	int ret, i;
 
 	if (!screen)
@@ -219,25 +219,25 @@ nv30_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 	switch (dev->chipset & 0xf0) {
 	case 0x30:
 		if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
-			rankine_class = 0x0397;
+			eng3d_class = 0x0397;
 		else
 		if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
-			rankine_class = 0x0697;
+			eng3d_class = 0x0697;
 		else
 		if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
-			rankine_class = 0x0497;
+			eng3d_class = 0x0497;
 		break;
 	default:
 		break;
 	}
 
-	if (!rankine_class) {
+	if (!eng3d_class) {
 		NOUVEAU_ERR("Unknown nv3x chipset: nv%02x\n", dev->chipset);
 		return NULL;
 	}
 
-	ret = nouveau_grobj_alloc(chan, 0xbeef3097, rankine_class,
-				  &screen->rankine);
+	ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class,
+				  &screen->eng3d);
 	if (ret) {
 		NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 		return FALSE;
@@ -277,80 +277,80 @@ nv30_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 		return NULL;
 	}
 
-	/* Static rankine initialisation */
+	/* Static eng3d initialisation */
 	so = so_new(36, 60, 0);
-	so_method(so, screen->rankine, NV34TCL_DMA_NOTIFY, 1);
+	so_method(so, screen->eng3d, NV34TCL_DMA_NOTIFY, 1);
 	so_data  (so, screen->sync->handle);
-	so_method(so, screen->rankine, NV34TCL_DMA_TEXTURE0, 2);
+	so_method(so, screen->eng3d, NV34TCL_DMA_TEXTURE0, 2);
 	so_data  (so, chan->vram->handle);
 	so_data  (so, chan->gart->handle);
-	so_method(so, screen->rankine, NV34TCL_DMA_COLOR1, 1);
+	so_method(so, screen->eng3d, NV34TCL_DMA_COLOR1, 1);
 	so_data  (so, chan->vram->handle);
-	so_method(so, screen->rankine, NV34TCL_DMA_COLOR0, 2);
+	so_method(so, screen->eng3d, NV34TCL_DMA_COLOR0, 2);
 	so_data  (so, chan->vram->handle);
 	so_data  (so, chan->vram->handle);
-	so_method(so, screen->rankine, NV34TCL_DMA_VTXBUF0, 2);
+	so_method(so, screen->eng3d, NV34TCL_DMA_VTXBUF0, 2);
 	so_data  (so, chan->vram->handle);
 	so_data  (so, chan->gart->handle);
-/*	so_method(so, screen->rankine, NV34TCL_DMA_FENCE, 2);
+/*	so_method(so, screen->eng3d, NV34TCL_DMA_FENCE, 2);
 	so_data  (so, 0);
 	so_data  (so, screen->query->handle);*/
-	so_method(so, screen->rankine, NV34TCL_DMA_IN_MEMORY7, 1);
+	so_method(so, screen->eng3d, NV34TCL_DMA_IN_MEMORY7, 1);
 	so_data  (so, chan->vram->handle);
-	so_method(so, screen->rankine, NV34TCL_DMA_IN_MEMORY8, 1);
+	so_method(so, screen->eng3d, NV34TCL_DMA_IN_MEMORY8, 1);
 	so_data  (so, chan->vram->handle);
 
 	for (i=1; i<8; i++) {
-		so_method(so, screen->rankine, NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1);
+		so_method(so, screen->eng3d, NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1);
 		so_data  (so, 0);
-		so_method(so, screen->rankine, NV34TCL_VIEWPORT_CLIP_VERT(i), 1);
+		so_method(so, screen->eng3d, NV34TCL_VIEWPORT_CLIP_VERT(i), 1);
 		so_data  (so, 0);
 	}
 
-	so_method(so, screen->rankine, 0x220, 1);
+	so_method(so, screen->eng3d, 0x220, 1);
 	so_data  (so, 1);
 
-	so_method(so, screen->rankine, 0x03b0, 1);
+	so_method(so, screen->eng3d, 0x03b0, 1);
 	so_data  (so, 0x00100000);
-	so_method(so, screen->rankine, 0x1454, 1);
+	so_method(so, screen->eng3d, 0x1454, 1);
 	so_data  (so, 0);
-	so_method(so, screen->rankine, 0x1d80, 1);
+	so_method(so, screen->eng3d, 0x1d80, 1);
 	so_data  (so, 3);
-	so_method(so, screen->rankine, 0x1450, 1);
+	so_method(so, screen->eng3d, 0x1450, 1);
 	so_data  (so, 0x00030004);
 
 	/* NEW */
-	so_method(so, screen->rankine, 0x1e98, 1);
+	so_method(so, screen->eng3d, 0x1e98, 1);
 	so_data  (so, 0);
-	so_method(so, screen->rankine, 0x17e0, 3);
+	so_method(so, screen->eng3d, 0x17e0, 3);
 	so_data  (so, fui(0.0));
 	so_data  (so, fui(0.0));
 	so_data  (so, fui(1.0));
-	so_method(so, screen->rankine, 0x1f80, 16);
+	so_method(so, screen->eng3d, 0x1f80, 16);
 	for (i=0; i<16; i++) {
 		so_data  (so, (i==8) ? 0x0000ffff : 0);
 	}
 
-	so_method(so, screen->rankine, 0x120, 3);
+	so_method(so, screen->eng3d, 0x120, 3);
 	so_data  (so, 0);
 	so_data  (so, 1);
 	so_data  (so, 2);
 
-	so_method(so, screen->rankine, 0x1d88, 1);
+	so_method(so, screen->eng3d, 0x1d88, 1);
 	so_data  (so, 0x00001200);
 
-	so_method(so, screen->rankine, NV34TCL_RC_ENABLE, 1);
+	so_method(so, screen->eng3d, NV34TCL_RC_ENABLE, 1);
 	so_data  (so, 0);
 
-	so_method(so, screen->rankine, NV34TCL_DEPTH_RANGE_NEAR, 2);
+	so_method(so, screen->eng3d, NV34TCL_DEPTH_RANGE_NEAR, 2);
 	so_data  (so, fui(0.0));
 	so_data  (so, fui(1.0));
 
-	so_method(so, screen->rankine, NV34TCL_MULTISAMPLE_CONTROL, 1);
+	so_method(so, screen->eng3d, NV34TCL_MULTISAMPLE_CONTROL, 1);
 	so_data  (so, 0xffff0000);
 
 	/* enables use of vp rather than fixed-function somehow */
-	so_method(so, screen->rankine, 0x1e94, 1);
+	so_method(so, screen->eng3d, 0x1e94, 1);
 	so_data  (so, 0x13);
 
 	so_emit(chan, so);
diff --git a/src/gallium/drivers/nv30/nv30_screen.h b/src/gallium/drivers/nv30/nv30_screen.h
index b7856cdf00..69a94593f9 100644
--- a/src/gallium/drivers/nv30/nv30_screen.h
+++ b/src/gallium/drivers/nv30/nv30_screen.h
@@ -14,7 +14,7 @@ struct nv30_screen {
 
 	/* HW graphics objects */
 	struct nv04_surface_2d *eng2d;
-	struct nouveau_grobj *rankine;
+	struct nouveau_grobj *eng3d;
 	struct nouveau_notifier *sync;
 
 	/* Query object resources */
diff --git a/src/gallium/drivers/nv30/nv30_state.c b/src/gallium/drivers/nv30/nv30_state.c
index 24b15a63ac..330448000b 100644
--- a/src/gallium/drivers/nv30/nv30_state.c
+++ b/src/gallium/drivers/nv30/nv30_state.c
@@ -12,12 +12,12 @@ nv30_blend_state_create(struct pipe_context *pipe,
 			const struct pipe_blend_state *cso)
 {
 	struct nv30_context *nv30 = nv30_context(pipe);
-	struct nouveau_grobj *rankine = nv30->screen->rankine;
+	struct nouveau_grobj *eng3d = nv30->screen->eng3d;
 	struct nv30_blend_state *bso = CALLOC(1, sizeof(*bso));
 	struct nouveau_stateobj *so = so_new(5, 8, 0);
 
 	if (cso->rt[0].blend_enable) {
-		so_method(so, rankine, NV34TCL_BLEND_FUNC_ENABLE, 3);
+		so_method(so, eng3d, NV34TCL_BLEND_FUNC_ENABLE, 3);
 		so_data  (so, 1);
 		so_data  (so, (nvgl_blend_func(cso->rt[0].alpha_src_factor) << 16) |
 			       nvgl_blend_func(cso->rt[0].rgb_src_factor));
@@ -25,29 +25,29 @@ nv30_blend_state_create(struct pipe_context *pipe,
 			      nvgl_blend_func(cso->rt[0].rgb_dst_factor));
 		/* FIXME: Gallium assumes GL_EXT_blend_func_separate.
 		   It is not the case for NV30 */
-		so_method(so, rankine, NV34TCL_BLEND_EQUATION, 1);
+		so_method(so, eng3d, NV34TCL_BLEND_EQUATION, 1);
 		so_data  (so, nvgl_blend_eqn(cso->rt[0].rgb_func));
 	} else {
-		so_method(so, rankine, NV34TCL_BLEND_FUNC_ENABLE, 1);
+		so_method(so, eng3d, NV34TCL_BLEND_FUNC_ENABLE, 1);
 		so_data  (so, 0);
 	}
 
-	so_method(so, rankine, NV34TCL_COLOR_MASK, 1);
+	so_method(so, eng3d, NV34TCL_COLOR_MASK, 1);
 	so_data  (so, (((cso->rt[0].colormask & PIPE_MASK_A) ? (0x01 << 24) : 0) |
 		       ((cso->rt[0].colormask & PIPE_MASK_R) ? (0x01 << 16) : 0) |
 		       ((cso->rt[0].colormask & PIPE_MASK_G) ? (0x01 <<  8) : 0) |
 		       ((cso->rt[0].colormask & PIPE_MASK_B) ? (0x01 <<  0) : 0)));
 
 	if (cso->logicop_enable) {
-		so_method(so, rankine, NV34TCL_COLOR_LOGIC_OP_ENABLE, 2);
+		so_method(so, eng3d, NV34TCL_COLOR_LOGIC_OP_ENABLE, 2);
 		so_data  (so, 1);
 		so_data  (so, nvgl_logicop_func(cso->logicop_func));
 	} else {
-		so_method(so, rankine, NV34TCL_COLOR_LOGIC_OP_ENABLE, 1);
+		so_method(so, eng3d, NV34TCL_COLOR_LOGIC_OP_ENABLE, 1);
 		so_data  (so, 0);
 	}
 
-	so_method(so, rankine, NV34TCL_DITHER_ENABLE, 1);
+	so_method(so, eng3d, NV34TCL_DITHER_ENABLE, 1);
 	so_data  (so, cso->dither ? 1 : 0);
 
 	so_ref(so, &bso->so);
@@ -301,7 +301,7 @@ nv30_rasterizer_state_create(struct pipe_context *pipe,
 	struct nv30_context *nv30 = nv30_context(pipe);
 	struct nv30_rasterizer_state *rsso = CALLOC(1, sizeof(*rsso));
 	struct nouveau_stateobj *so = so_new(9, 19, 0);
-	struct nouveau_grobj *rankine = nv30->screen->rankine;
+	struct nouveau_grobj *eng3d = nv30->screen->eng3d;
 
 	/*XXX: ignored:
 	 * 	light_twoside
@@ -309,22 +309,22 @@ nv30_rasterizer_state_create(struct pipe_context *pipe,
 	 * 	multisample
 	 */
 
-	so_method(so, rankine, NV34TCL_SHADE_MODEL, 1);
+	so_method(so, eng3d, NV34TCL_SHADE_MODEL, 1);
 	so_data  (so, cso->flatshade ? NV34TCL_SHADE_MODEL_FLAT :
 				       NV34TCL_SHADE_MODEL_SMOOTH);
 
-	so_method(so, rankine, NV34TCL_LINE_WIDTH, 2);
+	so_method(so, eng3d, NV34TCL_LINE_WIDTH, 2);
 	so_data  (so, (unsigned char)(cso->line_width * 8.0) & 0xff);
 	so_data  (so, cso->line_smooth ? 1 : 0);
-	so_method(so, rankine, NV34TCL_LINE_STIPPLE_ENABLE, 2);
+	so_method(so, eng3d, NV34TCL_LINE_STIPPLE_ENABLE, 2);
 	so_data  (so, cso->line_stipple_enable ? 1 : 0);
 	so_data  (so, (cso->line_stipple_pattern << 16) |
 		       cso->line_stipple_factor);
 
-	so_method(so, rankine, NV34TCL_POINT_SIZE, 1);
+	so_method(so, eng3d, NV34TCL_POINT_SIZE, 1);
 	so_data  (so, fui(cso->point_size));
 
-	so_method(so, rankine, NV34TCL_POLYGON_MODE_FRONT, 6);
+	so_method(so, eng3d, NV34TCL_POLYGON_MODE_FRONT, 6);
 	if (cso->front_winding == PIPE_WINDING_CCW) {
 		so_data(so, nvgl_polygon_mode(cso->fill_ccw));
 		so_data(so, nvgl_polygon_mode(cso->fill_cw));
@@ -365,10 +365,10 @@ nv30_rasterizer_state_create(struct pipe_context *pipe,
 	so_data(so, cso->poly_smooth ? 1 : 0);
 	so_data(so, (cso->cull_mode != PIPE_WINDING_NONE) ? 1 : 0);
 
-	so_method(so, rankine, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
+	so_method(so, eng3d, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
 	so_data  (so, cso->poly_stipple_enable ? 1 : 0);
 
-	so_method(so, rankine, NV34TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
+	so_method(so, eng3d, NV34TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
 	if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_POINT) ||
 	    (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_POINT))
 		so_data(so, 1);
@@ -385,12 +385,12 @@ nv30_rasterizer_state_create(struct pipe_context *pipe,
 	else
 		so_data(so, 0);
 	if (cso->offset_cw || cso->offset_ccw) {
-		so_method(so, rankine, NV34TCL_POLYGON_OFFSET_FACTOR, 2);
+		so_method(so, eng3d, NV34TCL_POLYGON_OFFSET_FACTOR, 2);
 		so_data  (so, fui(cso->offset_scale));
 		so_data  (so, fui(cso->offset_units * 2));
 	}
 
-	so_method(so, rankine, NV34TCL_POINT_SPRITE, 1);
+	so_method(so, eng3d, NV34TCL_POINT_SPRITE, 1);
 	if (cso->point_quad_rasterization) {
 		unsigned psctl = (1 << 0), i;
 
@@ -436,45 +436,45 @@ nv30_depth_stencil_alpha_state_create(struct pipe_context *pipe,
 	struct nv30_context *nv30 = nv30_context(pipe);
 	struct nv30_zsa_state *zsaso = CALLOC(1, sizeof(*zsaso));
 	struct nouveau_stateobj *so = so_new(6, 20, 0);
-	struct nouveau_grobj *rankine = nv30->screen->rankine;
+	struct nouveau_grobj *eng3d = nv30->screen->eng3d;
 
-	so_method(so, rankine, NV34TCL_DEPTH_FUNC, 3);
+	so_method(so, eng3d, NV34TCL_DEPTH_FUNC, 3);
 	so_data  (so, nvgl_comparison_op(cso->depth.func));
 	so_data  (so, cso->depth.writemask ? 1 : 0);
 	so_data  (so, cso->depth.enabled ? 1 : 0);
 
-	so_method(so, rankine, NV34TCL_ALPHA_FUNC_ENABLE, 3);
+	so_method(so, eng3d, NV34TCL_ALPHA_FUNC_ENABLE, 3);
 	so_data  (so, cso->alpha.enabled ? 1 : 0);
 	so_data  (so, nvgl_comparison_op(cso->alpha.func));
 	so_data  (so, float_to_ubyte(cso->alpha.ref_value));
 
 	if (cso->stencil[0].enabled) {
-		so_method(so, rankine, NV34TCL_STENCIL_FRONT_ENABLE, 3);
+		so_method(so, eng3d, NV34TCL_STENCIL_FRONT_ENABLE, 3);
 		so_data  (so, cso->stencil[0].enabled ? 1 : 0);
 		so_data  (so, cso->stencil[0].writemask);
 		so_data  (so, nvgl_comparison_op(cso->stencil[0].func));
-		so_method(so, rankine, NV34TCL_STENCIL_FRONT_FUNC_MASK, 4);
+		so_method(so, eng3d, NV34TCL_STENCIL_FRONT_FUNC_MASK, 4);
 		so_data  (so, cso->stencil[0].valuemask);
 		so_data  (so, nvgl_stencil_op(cso->stencil[0].fail_op));
 		so_data  (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
 		so_data  (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
 	} else {
-		so_method(so, rankine, NV34TCL_STENCIL_FRONT_ENABLE, 1);
+		so_method(so, eng3d, NV34TCL_STENCIL_FRONT_ENABLE, 1);
 		so_data  (so, 0);
 	}
 
 	if (cso->stencil[1].enabled) {
-		so_method(so, rankine, NV34TCL_STENCIL_BACK_ENABLE, 3);
+		so_method(so, eng3d, NV34TCL_STENCIL_BACK_ENABLE, 3);
 		so_data  (so, cso->stencil[1].enabled ? 1 : 0);
 		so_data  (so, cso->stencil[1].writemask);
 		so_data  (so, nvgl_comparison_op(cso->stencil[1].func));
-		so_method(so, rankine, NV34TCL_STENCIL_BACK_FUNC_MASK, 4);
+		so_method(so, eng3d, NV34TCL_STENCIL_BACK_FUNC_MASK, 4);
 		so_data  (so, cso->stencil[1].valuemask);
 		so_data  (so, nvgl_stencil_op(cso->stencil[1].fail_op));
 		so_data  (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
 		so_data  (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
 	} else {
-		so_method(so, rankine, NV34TCL_STENCIL_BACK_ENABLE, 1);
+		so_method(so, eng3d, NV34TCL_STENCIL_BACK_ENABLE, 1);
 		so_data  (so, 0);
 	}
 
diff --git a/src/gallium/drivers/nv30/nv30_state_blend.c b/src/gallium/drivers/nv30/nv30_state_blend.c
index c36d58c040..eb0199cf65 100644
--- a/src/gallium/drivers/nv30/nv30_state_blend.c
+++ b/src/gallium/drivers/nv30/nv30_state_blend.c
@@ -21,7 +21,7 @@ nv30_state_blend_colour_validate(struct nv30_context *nv30)
 	struct nouveau_stateobj *so = so_new(1, 1, 0);
 	struct pipe_blend_color *bcol = &nv30->blend_colour;
 
-	so_method(so, nv30->screen->rankine, NV34TCL_BLEND_COLOR, 1);
+	so_method(so, nv30->screen->eng3d, NV34TCL_BLEND_COLOR, 1);
 	so_data  (so, ((float_to_ubyte(bcol->color[3]) << 24) |
 		       (float_to_ubyte(bcol->color[0]) << 16) |
 		       (float_to_ubyte(bcol->color[1]) <<  8) |
diff --git a/src/gallium/drivers/nv30/nv30_state_fb.c b/src/gallium/drivers/nv30/nv30_state_fb.c
index f7fe9833c7..23d17c0c60 100644
--- a/src/gallium/drivers/nv30/nv30_state_fb.c
+++ b/src/gallium/drivers/nv30/nv30_state_fb.c
@@ -6,7 +6,7 @@ nv30_state_framebuffer_validate(struct nv30_context *nv30)
 {
 	struct pipe_framebuffer_state *fb = &nv30->framebuffer;
 	struct nouveau_channel *chan = nv30->screen->base.channel;
-	struct nouveau_grobj *rankine = nv30->screen->rankine;
+	struct nouveau_grobj *eng3d = nv30->screen->eng3d;
 	struct nv04_surface *rt[2], *zeta = NULL;
 	uint32_t rt_enable = 0, rt_format = 0;
 	int i, colour_format = 0, zeta_format = 0, depth_only = 0;
@@ -110,10 +110,10 @@ nv30_state_framebuffer_validate(struct nv30_context *nv30)
 		}
 
 		nv30mt = (struct nv30_miptree *) rt0->base.texture;
-		so_method(so, rankine, NV34TCL_DMA_COLOR0, 1);
+		so_method(so, eng3d, NV34TCL_DMA_COLOR0, 1);
 		so_reloc (so, nouveau_bo(nv30mt->buffer), 0, rt_flags | NOUVEAU_BO_OR,
 			      chan->vram->handle, chan->gart->handle);
-		so_method(so, rankine, NV34TCL_COLOR0_PITCH, 2);
+		so_method(so, eng3d, NV34TCL_COLOR0_PITCH, 2);
 		so_data  (so, pitch);
 		so_reloc (so, nouveau_bo(nv30mt->buffer), rt0->base.offset,
 			      rt_flags | NOUVEAU_BO_LOW, 0, 0);
@@ -121,10 +121,10 @@ nv30_state_framebuffer_validate(struct nv30_context *nv30)
 
 	if (rt_enable & NV34TCL_RT_ENABLE_COLOR1) {
 		nv30mt = (struct nv30_miptree *)rt[1]->base.texture;
-		so_method(so, rankine, NV34TCL_DMA_COLOR1, 1);
+		so_method(so, eng3d, NV34TCL_DMA_COLOR1, 1);
 		so_reloc (so, nouveau_bo(nv30mt->buffer), 0, rt_flags | NOUVEAU_BO_OR,
 			      chan->vram->handle, chan->gart->handle);
-		so_method(so, rankine, NV34TCL_COLOR1_OFFSET, 2);
+		so_method(so, eng3d, NV34TCL_COLOR1_OFFSET, 2);
 		so_reloc (so, nouveau_bo(nv30mt->buffer), rt[1]->base.offset,
 			      rt_flags | NOUVEAU_BO_LOW, 0, 0);
 		so_data  (so, rt[1]->pitch);
@@ -132,31 +132,31 @@ nv30_state_framebuffer_validate(struct nv30_context *nv30)
 
 	if (zeta_format) {
 		nv30mt = (struct nv30_miptree *)zeta->base.texture;
-		so_method(so, rankine, NV34TCL_DMA_ZETA, 1);
+		so_method(so, eng3d, NV34TCL_DMA_ZETA, 1);
 		so_reloc (so, nouveau_bo(nv30mt->buffer), 0, rt_flags | NOUVEAU_BO_OR,
 			      chan->vram->handle, chan->gart->handle);
-		so_method(so, rankine, NV34TCL_ZETA_OFFSET, 1);
+		so_method(so, eng3d, NV34TCL_ZETA_OFFSET, 1);
 		so_reloc (so, nouveau_bo(nv30mt->buffer), zeta->base.offset,
 			      rt_flags | NOUVEAU_BO_LOW, 0, 0);
 		/* TODO: allocate LMA depth buffer */
 	}
 
-	so_method(so, rankine, NV34TCL_RT_ENABLE, 1);
+	so_method(so, eng3d, NV34TCL_RT_ENABLE, 1);
 	so_data  (so, rt_enable);
-	so_method(so, rankine, NV34TCL_RT_HORIZ, 3);
+	so_method(so, eng3d, NV34TCL_RT_HORIZ, 3);
 	so_data  (so, (w << 16) | 0);
 	so_data  (so, (h << 16) | 0);
 	so_data  (so, rt_format);
-	so_method(so, rankine, NV34TCL_VIEWPORT_HORIZ, 2);
+	so_method(so, eng3d, NV34TCL_VIEWPORT_HORIZ, 2);
 	so_data  (so, (w << 16) | 0);
 	so_data  (so, (h << 16) | 0);
-	so_method(so, rankine, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2);
+	so_method(so, eng3d, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2);
 	so_data  (so, ((w - 1) << 16) | 0);
 	so_data  (so, ((h - 1) << 16) | 0);
-	so_method(so, rankine, 0x1d88, 1);
+	so_method(so, eng3d, 0x1d88, 1);
 	so_data  (so, (1 << 12) | h);
 	/* Wonder why this is needed, context should all be set to zero on init */
-	so_method(so, rankine, NV34TCL_VIEWPORT_TX_ORIGIN, 1);
+	so_method(so, eng3d, NV34TCL_VIEWPORT_TX_ORIGIN, 1);
 	so_data  (so, 0);
 
 	so_ref(so, &nv30->state.hw[NV30_STATE_FB]);
diff --git a/src/gallium/drivers/nv30/nv30_state_scissor.c b/src/gallium/drivers/nv30/nv30_state_scissor.c
index ba61a9e24a..f58bb0161e 100644
--- a/src/gallium/drivers/nv30/nv30_state_scissor.c
+++ b/src/gallium/drivers/nv30/nv30_state_scissor.c
@@ -13,7 +13,7 @@ nv30_state_scissor_validate(struct nv30_context *nv30)
 	nv30->state.scissor_enabled = rast->scissor;
 
 	so = so_new(1, 2, 0);
-	so_method(so, nv30->screen->rankine, NV34TCL_SCISSOR_HORIZ, 2);
+	so_method(so, nv30->screen->eng3d, NV34TCL_SCISSOR_HORIZ, 2);
 	if (nv30->state.scissor_enabled) {
 		so_data  (so, ((s->maxx - s->minx) << 16) | s->minx);
 		so_data  (so, ((s->maxy - s->miny) << 16) | s->miny);
diff --git a/src/gallium/drivers/nv30/nv30_state_stipple.c b/src/gallium/drivers/nv30/nv30_state_stipple.c
index ed520a4f43..46a6975438 100644
--- a/src/gallium/drivers/nv30/nv30_state_stipple.c
+++ b/src/gallium/drivers/nv30/nv30_state_stipple.c
@@ -4,7 +4,7 @@ static boolean
 nv30_state_stipple_validate(struct nv30_context *nv30)
 {
 	struct pipe_rasterizer_state *rast = &nv30->rasterizer->pipe;
-	struct nouveau_grobj *rankine = nv30->screen->rankine;
+	struct nouveau_grobj *eng3d = nv30->screen->eng3d;
 	struct nouveau_stateobj *so;
 
 	if (nv30->state.hw[NV30_STATE_STIPPLE] &&
@@ -15,14 +15,14 @@ nv30_state_stipple_validate(struct nv30_context *nv30)
 		unsigned i;
 
 		so = so_new(2, 33, 0);
-		so_method(so, rankine, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
+		so_method(so, eng3d, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
 		so_data  (so, 1);
-		so_method(so, rankine, NV34TCL_POLYGON_STIPPLE_PATTERN(0), 32);
+		so_method(so, eng3d, NV34TCL_POLYGON_STIPPLE_PATTERN(0), 32);
 		for (i = 0; i < 32; i++)
 			so_data(so, nv30->stipple[i]);
 	} else {
 		so = so_new(1, 1, 0);
-		so_method(so, rankine, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
+		so_method(so, eng3d, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
 		so_data  (so, 0);
 	}
 
diff --git a/src/gallium/drivers/nv30/nv30_state_viewport.c b/src/gallium/drivers/nv30/nv30_state_viewport.c
index 6fccd6b60e..66fc112f3c 100644
--- a/src/gallium/drivers/nv30/nv30_state_viewport.c
+++ b/src/gallium/drivers/nv30/nv30_state_viewport.c
@@ -11,7 +11,7 @@ nv30_state_viewport_validate(struct nv30_context *nv30)
 		return FALSE;
 
 	so = so_new(3, 10, 0);
-	so_method(so, nv30->screen->rankine,
+	so_method(so, nv30->screen->eng3d,
 		  NV34TCL_VIEWPORT_TRANSLATE_X, 8);
 	so_data  (so, fui(vpt->translate[0]));
 	so_data  (so, fui(vpt->translate[1]));
@@ -21,11 +21,11 @@ nv30_state_viewport_validate(struct nv30_context *nv30)
 	so_data  (so, fui(vpt->scale[1]));
 	so_data  (so, fui(vpt->scale[2]));
 	so_data  (so, fui(vpt->scale[3]));
-/*	so_method(so, nv30->screen->rankine, 0x1d78, 1);
+/*	so_method(so, nv30->screen->eng3d, 0x1d78, 1);
 	so_data  (so, 1);
 */
 	/* TODO/FIXME: never saw value 0x0110 in renouveau dumps, only 0x0001 */
-	so_method(so, nv30->screen->rankine, 0x1d78, 1);
+	so_method(so, nv30->screen->eng3d, 0x1d78, 1);
 	so_data  (so, 1);
 
 	so_ref(so, &nv30->state.hw[NV30_STATE_VIEWPORT]);
diff --git a/src/gallium/drivers/nv30/nv30_state_zsa.c b/src/gallium/drivers/nv30/nv30_state_zsa.c
index 88cd74f180..b0aac8ee46 100644
--- a/src/gallium/drivers/nv30/nv30_state_zsa.c
+++ b/src/gallium/drivers/nv30/nv30_state_zsa.c
@@ -22,9 +22,9 @@ nv30_state_sr_validate(struct nv30_context *nv30)
 	struct nouveau_stateobj *so = so_new(2, 2, 0);
 	struct pipe_stencil_ref *sr = &nv30->stencil_ref;
 
-	so_method(so, nv30->screen->rankine, NV34TCL_STENCIL_FRONT_FUNC_REF, 1);
+	so_method(so, nv30->screen->eng3d, NV34TCL_STENCIL_FRONT_FUNC_REF, 1);
 	so_data  (so, sr->ref_value[0]);
-	so_method(so, nv30->screen->rankine, NV34TCL_STENCIL_BACK_FUNC_REF, 1);
+	so_method(so, nv30->screen->eng3d, NV34TCL_STENCIL_BACK_FUNC_REF, 1);
 	so_data  (so, sr->ref_value[1]);
 
 	so_ref(so, &nv30->state.hw[NV30_STATE_SR]);
diff --git a/src/gallium/drivers/nv30/nv30_vbo.c b/src/gallium/drivers/nv30/nv30_vbo.c
index f3856bb5a5..c7f119e90a 100644
--- a/src/gallium/drivers/nv30/nv30_vbo.c
+++ b/src/gallium/drivers/nv30/nv30_vbo.c
@@ -111,7 +111,7 @@ nv30_vbo_static_attrib(struct nv30_context *nv30, struct nouveau_stateobj *so,
 		       struct pipe_vertex_buffer *vb)
 {
 	struct pipe_screen *pscreen = nv30->pipe.screen;
-	struct nouveau_grobj *rankine = nv30->screen->rankine;
+	struct nouveau_grobj *eng3d = nv30->screen->eng3d;
 	unsigned type, ncomp;
 	void *map;
 
@@ -128,25 +128,25 @@ nv30_vbo_static_attrib(struct nv30_context *nv30, struct nouveau_stateobj *so,
 
 		switch (ncomp) {
 		case 4:
-			so_method(so, rankine, NV34TCL_VTX_ATTR_4F_X(attrib), 4);
+			so_method(so, eng3d, NV34TCL_VTX_ATTR_4F_X(attrib), 4);
 			so_data  (so, fui(v[0]));
 			so_data  (so, fui(v[1]));
 			so_data  (so, fui(v[2]));
 			so_data  (so, fui(v[3]));
 			break;
 		case 3:
-			so_method(so, rankine, NV34TCL_VTX_ATTR_3F_X(attrib), 3);
+			so_method(so, eng3d, NV34TCL_VTX_ATTR_3F_X(attrib), 3);
 			so_data  (so, fui(v[0]));
 			so_data  (so, fui(v[1]));
 			so_data  (so, fui(v[2]));
 			break;
 		case 2:
-			so_method(so, rankine, NV34TCL_VTX_ATTR_2F_X(attrib), 2);
+			so_method(so, eng3d, NV34TCL_VTX_ATTR_2F_X(attrib), 2);
 			so_data  (so, fui(v[0]));
 			so_data  (so, fui(v[1]));
 			break;
 		case 1:
-			so_method(so, rankine, NV34TCL_VTX_ATTR_1F(attrib), 1);
+			so_method(so, eng3d, NV34TCL_VTX_ATTR_1F(attrib), 1);
 			so_data  (so, fui(v[0]));
 			break;
 		default:
@@ -171,7 +171,7 @@ nv30_draw_arrays(struct pipe_context *pipe,
 	struct nv30_context *nv30 = nv30_context(pipe);
 	struct nv30_screen *screen = nv30->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *rankine = screen->rankine;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 	unsigned restart = 0;
 
 	nv30_vbo_set_idxbuf(nv30, NULL, 0);
@@ -193,12 +193,12 @@ nv30_draw_arrays(struct pipe_context *pipe,
 			continue;
 		}
 
-		BEGIN_RING(chan, rankine, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, nvgl_primitive(mode));
 
 		nr = (vc & 0xff);
 		if (nr) {
-			BEGIN_RING(chan, rankine, NV34TCL_VB_VERTEX_BATCH, 1);
+			BEGIN_RING(chan, eng3d, NV34TCL_VB_VERTEX_BATCH, 1);
 			OUT_RING  (chan, ((nr - 1) << 24) | start);
 			start += nr;
 		}
@@ -209,14 +209,14 @@ nv30_draw_arrays(struct pipe_context *pipe,
 
 			nr -= push;
 
-			BEGIN_RING_NI(chan, rankine, NV34TCL_VB_VERTEX_BATCH, push);
+			BEGIN_RING_NI(chan, eng3d, NV34TCL_VB_VERTEX_BATCH, push);
 			while (push--) {
 				OUT_RING(chan, ((0x100 - 1) << 24) | start);
 				start += 0x100;
 			}
 		}
 
-		BEGIN_RING(chan, rankine, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, 0);
 
 		count -= vc;
@@ -232,7 +232,7 @@ nv30_draw_elements_u08(struct nv30_context *nv30, void *ib,
 {
 	struct nv30_screen *screen = nv30->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *rankine = screen->rankine;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 
 	while (count) {
 		uint8_t *elts = (uint8_t *)ib + start;
@@ -248,11 +248,11 @@ nv30_draw_elements_u08(struct nv30_context *nv30, void *ib,
 		}
 		count -= vc;
 
-		BEGIN_RING(chan, rankine, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, nvgl_primitive(mode));
 
 		if (vc & 1) {
-			BEGIN_RING(chan, rankine, NV34TCL_VB_ELEMENT_U32, 1);
+			BEGIN_RING(chan, eng3d, NV34TCL_VB_ELEMENT_U32, 1);
 			OUT_RING  (chan, elts[0]);
 			elts++; vc--;
 		}
@@ -262,7 +262,7 @@ nv30_draw_elements_u08(struct nv30_context *nv30, void *ib,
 
 			push = MIN2(vc, 2047 * 2);
 
-			BEGIN_RING_NI(chan, rankine, NV34TCL_VB_ELEMENT_U16, push >> 1);
+			BEGIN_RING_NI(chan, eng3d, NV34TCL_VB_ELEMENT_U16, push >> 1);
 			for (i = 0; i < push; i+=2)
 				OUT_RING(chan, (elts[i+1] << 16) | elts[i]);
 
@@ -270,7 +270,7 @@ nv30_draw_elements_u08(struct nv30_context *nv30, void *ib,
 			elts += push;
 		}
 
-		BEGIN_RING(chan, rankine, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, 0);
 
 		start = restart;
@@ -283,7 +283,7 @@ nv30_draw_elements_u16(struct nv30_context *nv30, void *ib,
 {
 	struct nv30_screen *screen = nv30->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *rankine = screen->rankine;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 
 	while (count) {
 		uint16_t *elts = (uint16_t *)ib + start;
@@ -299,11 +299,11 @@ nv30_draw_elements_u16(struct nv30_context *nv30, void *ib,
 		}
 		count -= vc;
 
-		BEGIN_RING(chan, rankine, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, nvgl_primitive(mode));
 
 		if (vc & 1) {
-			BEGIN_RING(chan, rankine, NV34TCL_VB_ELEMENT_U32, 1);
+			BEGIN_RING(chan, eng3d, NV34TCL_VB_ELEMENT_U32, 1);
 			OUT_RING  (chan, elts[0]);
 			elts++; vc--;
 		}
@@ -313,7 +313,7 @@ nv30_draw_elements_u16(struct nv30_context *nv30, void *ib,
 
 			push = MIN2(vc, 2047 * 2);
 
-			BEGIN_RING_NI(chan, rankine, NV34TCL_VB_ELEMENT_U16, push >> 1);
+			BEGIN_RING_NI(chan, eng3d, NV34TCL_VB_ELEMENT_U16, push >> 1);
 			for (i = 0; i < push; i+=2)
 				OUT_RING(chan, (elts[i+1] << 16) | elts[i]);
 
@@ -321,7 +321,7 @@ nv30_draw_elements_u16(struct nv30_context *nv30, void *ib,
 			elts += push;
 		}
 
-		BEGIN_RING(chan, rankine, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, 0);
 
 		start = restart;
@@ -334,7 +334,7 @@ nv30_draw_elements_u32(struct nv30_context *nv30, void *ib,
 {
 	struct nv30_screen *screen = nv30->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *rankine = screen->rankine;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 
 	while (count) {
 		uint32_t *elts = (uint32_t *)ib + start;
@@ -350,20 +350,20 @@ nv30_draw_elements_u32(struct nv30_context *nv30, void *ib,
 		}
 		count -= vc;
 
-		BEGIN_RING(chan, rankine, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, nvgl_primitive(mode));
 
 		while (vc) {
 			push = MIN2(vc, 2047);
 
-			BEGIN_RING_NI(chan, rankine, NV34TCL_VB_ELEMENT_U32, push);
+			BEGIN_RING_NI(chan, eng3d, NV34TCL_VB_ELEMENT_U32, push);
 			OUT_RINGp    (chan, elts, push);
 
 			vc -= push;
 			elts += push;
 		}
 
-		BEGIN_RING(chan, rankine, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, 0);
 
 		start = restart;
@@ -410,7 +410,7 @@ nv30_draw_elements_vbo(struct pipe_context *pipe,
 	struct nv30_context *nv30 = nv30_context(pipe);
 	struct nv30_screen *screen = nv30->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *rankine = screen->rankine;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 	unsigned restart = 0;
 
 	while (count) {
@@ -425,12 +425,12 @@ nv30_draw_elements_vbo(struct pipe_context *pipe,
 			continue;
 		}
 
-		BEGIN_RING(chan, rankine, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, nvgl_primitive(mode));
 
 		nr = (vc & 0xff);
 		if (nr) {
-			BEGIN_RING(chan, rankine, NV34TCL_VB_INDEX_BATCH, 1);
+			BEGIN_RING(chan, eng3d, NV34TCL_VB_INDEX_BATCH, 1);
 			OUT_RING  (chan, ((nr - 1) << 24) | start);
 			start += nr;
 		}
@@ -441,14 +441,14 @@ nv30_draw_elements_vbo(struct pipe_context *pipe,
 
 			nr -= push;
 
-			BEGIN_RING_NI(chan, rankine, NV34TCL_VB_INDEX_BATCH, push);
+			BEGIN_RING_NI(chan, eng3d, NV34TCL_VB_INDEX_BATCH, push);
 			while (push--) {
 				OUT_RING(chan, ((0x100 - 1) << 24) | start);
 				start += 0x100;
 			}
 		}
 
-		BEGIN_RING(chan, rankine, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, 0);
 
 		count -= vc;
@@ -485,16 +485,16 @@ static boolean
 nv30_vbo_validate(struct nv30_context *nv30)
 {
 	struct nouveau_stateobj *vtxbuf, *vtxfmt, *sattr = NULL;
-	struct nouveau_grobj *rankine = nv30->screen->rankine;
+	struct nouveau_grobj *eng3d = nv30->screen->eng3d;
 	struct pipe_buffer *ib = nv30->idxbuf;
 	unsigned ib_format = nv30->idxbuf_format;
 	unsigned vb_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
 	int hw;
 
 	vtxbuf = so_new(3, 17, 18);
-	so_method(vtxbuf, rankine, NV34TCL_VTXBUF_ADDRESS(0), nv30->vtxelt->num_elements);
+	so_method(vtxbuf, eng3d, NV34TCL_VTXBUF_ADDRESS(0), nv30->vtxelt->num_elements);
 	vtxfmt = so_new(1, 16, 0);
-	so_method(vtxfmt, rankine, NV34TCL_VTXFMT(0), nv30->vtxelt->num_elements);
+	so_method(vtxfmt, eng3d, NV34TCL_VTXFMT(0), nv30->vtxelt->num_elements);
 
 	for (hw = 0; hw < nv30->vtxelt->num_elements; hw++) {
 		struct pipe_vertex_element *ve;
@@ -532,13 +532,13 @@ nv30_vbo_validate(struct nv30_context *nv30)
 	if (ib) {
 		struct nouveau_bo *bo = nouveau_bo(ib);
 
-		so_method(vtxbuf, rankine, NV34TCL_IDXBUF_ADDRESS, 2);
+		so_method(vtxbuf, eng3d, NV34TCL_IDXBUF_ADDRESS, 2);
 		so_reloc (vtxbuf, bo, 0, vb_flags | NOUVEAU_BO_LOW, 0, 0);
 		so_reloc (vtxbuf, bo, ib_format, vb_flags | NOUVEAU_BO_OR,
 				  0, NV34TCL_IDXBUF_FORMAT_DMA1);
 	}
 
-	so_method(vtxbuf, rankine, 0x1710, 1);
+	so_method(vtxbuf, eng3d, 0x1710, 1);
 	so_data  (vtxbuf, 0);
 
 	so_ref(vtxbuf, &nv30->state.hw[NV30_STATE_VTXBUF]);
diff --git a/src/gallium/drivers/nv30/nv30_vertprog.c b/src/gallium/drivers/nv30/nv30_vertprog.c
index 809be3712d..f0cecba4c4 100644
--- a/src/gallium/drivers/nv30/nv30_vertprog.c
+++ b/src/gallium/drivers/nv30/nv30_vertprog.c
@@ -652,7 +652,7 @@ nv30_vertprog_validate(struct nv30_context *nv30)
 	struct pipe_screen *pscreen = nv30->pipe.screen;
 	struct nv30_screen *screen = nv30->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *rankine = screen->rankine;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 	struct nv30_vertex_program *vp;
 	struct pipe_buffer *constbuf;
 	boolean upload_code = FALSE, upload_data = FALSE;
@@ -687,7 +687,7 @@ nv30_vertprog_validate(struct nv30_context *nv30)
 		}
 
 		so = so_new(1, 1, 0);
-		so_method(so, rankine, NV34TCL_VP_START_FROM_ID, 1);
+		so_method(so, eng3d, NV34TCL_VP_START_FROM_ID, 1);
 		so_data  (so, vp->exec->start);
 		so_ref(so, &vp->so);
 		so_ref(NULL, &so);
@@ -772,7 +772,7 @@ nv30_vertprog_validate(struct nv30_context *nv30)
 				       4 * sizeof(float));
 			}
 
-			BEGIN_RING(chan, rankine, NV34TCL_VP_UPLOAD_CONST_ID, 5);
+			BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_CONST_ID, 5);
 			OUT_RING  (chan, i + vp->data->start);
 			OUT_RINGp (chan, (uint32_t *)vpd->value, 4);
 		}
@@ -790,10 +790,10 @@ nv30_vertprog_validate(struct nv30_context *nv30)
 				vp->insns[i].data[2], vp->insns[i].data[3]);
 		}
 #endif
-		BEGIN_RING(chan, rankine, NV34TCL_VP_UPLOAD_FROM_ID, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_FROM_ID, 1);
 		OUT_RING  (chan, vp->exec->start);
 		for (i = 0; i < vp->nr_insns; i++) {
-			BEGIN_RING(chan, rankine, NV34TCL_VP_UPLOAD_INST(0), 4);
+			BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_INST(0), 4);
 			OUT_RINGp (chan, vp->insns[i].data, 4);
 		}
 	}
diff --git a/src/gallium/drivers/nv40/nv40_context.c b/src/gallium/drivers/nv40/nv40_context.c
index e828f17643..da35676fd5 100644
--- a/src/gallium/drivers/nv40/nv40_context.c
+++ b/src/gallium/drivers/nv40/nv40_context.c
@@ -11,12 +11,12 @@ nv40_flush(struct pipe_context *pipe, unsigned flags,
 	struct nv40_context *nv40 = nv40_context(pipe);
 	struct nv40_screen *screen = nv40->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *curie = screen->curie;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 
 	if (flags & PIPE_FLUSH_TEXTURE_CACHE) {
-		BEGIN_RING(chan, curie, 0x1fd8, 1);
+		BEGIN_RING(chan, eng3d, 0x1fd8, 1);
 		OUT_RING  (chan, 2);
-		BEGIN_RING(chan, curie, 0x1fd8, 1);
+		BEGIN_RING(chan, eng3d, 0x1fd8, 1);
 		OUT_RING  (chan, 1);
 	}
 
diff --git a/src/gallium/drivers/nv40/nv40_draw.c b/src/gallium/drivers/nv40/nv40_draw.c
index 849f24fe40..05d237d1bb 100644
--- a/src/gallium/drivers/nv40/nv40_draw.c
+++ b/src/gallium/drivers/nv40/nv40_draw.c
@@ -33,7 +33,7 @@ nv40_render_vertex(struct nv40_context *nv40, const struct vertex_header *v)
 {
 	struct nv40_screen *screen = nv40->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *curie = screen->curie;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 	unsigned i;
 
 	for (i = 0; i < nv40->swtnl.nr_attribs; i++) {
@@ -44,29 +44,29 @@ nv40_render_vertex(struct nv40_context *nv40, const struct vertex_header *v)
 		case EMIT_OMIT:
 			break;
 		case EMIT_1F:
-			BEGIN_RING(chan, curie, NV34TCL_VTX_ATTR_1F(hw), 1);
+			BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_1F(hw), 1);
 			OUT_RING  (chan, fui(v->data[idx][0]));
 			break;
 		case EMIT_2F:
-			BEGIN_RING(chan, curie, NV34TCL_VTX_ATTR_2F_X(hw), 2);
+			BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_2F_X(hw), 2);
 			OUT_RING  (chan, fui(v->data[idx][0]));
 			OUT_RING  (chan, fui(v->data[idx][1]));
 			break;
 		case EMIT_3F:
-			BEGIN_RING(chan, curie, NV34TCL_VTX_ATTR_3F_X(hw), 3);
+			BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_3F_X(hw), 3);
 			OUT_RING  (chan, fui(v->data[idx][0]));
 			OUT_RING  (chan, fui(v->data[idx][1]));
 			OUT_RING  (chan, fui(v->data[idx][2]));
 			break;
 		case EMIT_4F:
-			BEGIN_RING(chan, curie, NV34TCL_VTX_ATTR_4F_X(hw), 4);
+			BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_4F_X(hw), 4);
 			OUT_RING  (chan, fui(v->data[idx][0]));
 			OUT_RING  (chan, fui(v->data[idx][1]));
 			OUT_RING  (chan, fui(v->data[idx][2]));
 			OUT_RING  (chan, fui(v->data[idx][3]));
 			break;
 		case EMIT_4UB:
-			BEGIN_RING(chan, curie, NV34TCL_VTX_ATTR_4UB(hw), 1);
+			BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_4UB(hw), 1);
 			OUT_RING  (chan, pack_ub4(float_to_ubyte(v->data[idx][0]),
 					    float_to_ubyte(v->data[idx][1]),
 					    float_to_ubyte(v->data[idx][2]),
@@ -88,7 +88,7 @@ nv40_render_prim(struct draw_stage *stage, struct prim_header *prim,
 
 	struct nv40_screen *screen = nv40->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *curie = screen->curie;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 	unsigned i;
 
 	/* Ensure there's room for 4xfloat32 + potentially 3 begin/end */
@@ -104,11 +104,11 @@ nv40_render_prim(struct draw_stage *stage, struct prim_header *prim,
 	/* Switch primitive modes if necessary */
 	if (rs->prim != mode) {
 		if (rs->prim != NV34TCL_VERTEX_BEGIN_END_STOP) {
-			BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+			BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 			OUT_RING  (chan, NV34TCL_VERTEX_BEGIN_END_STOP);
 		}
 
-		BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, mode);
 		rs->prim = mode;
 	}
@@ -121,7 +121,7 @@ nv40_render_prim(struct draw_stage *stage, struct prim_header *prim,
 	 * off the primitive now.
 	 */
 	if (AVAIL_RING(chan) < ((count * 20) + 6)) {
-		BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, NV34TCL_VERTEX_BEGIN_END_STOP);
 		rs->prim = NV34TCL_VERTEX_BEGIN_END_STOP;
 	}
@@ -152,10 +152,10 @@ nv40_render_flush(struct draw_stage *draw, unsigned flags)
 	struct nv40_context *nv40 = rs->nv40;
 	struct nv40_screen *screen = nv40->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *curie = screen->curie;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 
 	if (rs->prim != NV34TCL_VERTEX_BEGIN_END_STOP) {
-		BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, NV34TCL_VERTEX_BEGIN_END_STOP);
 		rs->prim = NV34TCL_VERTEX_BEGIN_END_STOP;
 	}
diff --git a/src/gallium/drivers/nv40/nv40_fragprog.c b/src/gallium/drivers/nv40/nv40_fragprog.c
index d881fea6f5..3d08828bea 100644
--- a/src/gallium/drivers/nv40/nv40_fragprog.c
+++ b/src/gallium/drivers/nv40/nv40_fragprog.c
@@ -920,12 +920,12 @@ nv40_fragprog_validate(struct nv40_context *nv40)
 	nv40_fragprog_upload(nv40, fp);
 
 	so = so_new(2, 2, 1);
-	so_method(so, nv40->screen->curie, NV34TCL_FP_ACTIVE_PROGRAM, 1);
+	so_method(so, nv40->screen->eng3d, NV34TCL_FP_ACTIVE_PROGRAM, 1);
 	so_reloc (so, nouveau_bo(fp->buffer), 0, NOUVEAU_BO_VRAM |
 		      NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
 		      NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
 		      NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
-	so_method(so, nv40->screen->curie, NV34TCL_FP_CONTROL, 1);
+	so_method(so, nv40->screen->eng3d, NV34TCL_FP_CONTROL, 1);
 	so_data  (so, fp->fp_control);
 	so_ref(so, &fp->so);
 	so_ref(NULL, &so);
diff --git a/src/gallium/drivers/nv40/nv40_fragtex.c b/src/gallium/drivers/nv40/nv40_fragtex.c
index 44bf4333bd..4c26f3cb12 100644
--- a/src/gallium/drivers/nv40/nv40_fragtex.c
+++ b/src/gallium/drivers/nv40/nv40_fragtex.c
@@ -111,7 +111,7 @@ nv40_fragtex_build(struct nv40_context *nv40, int unit)
 	txs = tf->swizzle;
 
 	so = so_new(2, 9, 2);
-	so_method(so, nv40->screen->curie, NV34TCL_TX_OFFSET(unit), 8);
+	so_method(so, nv40->screen->eng3d, NV34TCL_TX_OFFSET(unit), 8);
 	so_reloc (so, bo, 0, tex_flags | NOUVEAU_BO_LOW, 0, 0);
 	so_reloc (so, bo, txf, tex_flags | NOUVEAU_BO_OR,
 		      NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1);
@@ -122,7 +122,7 @@ nv40_fragtex_build(struct nv40_context *nv40, int unit)
 	so_data  (so, (pt->width0 << NV34TCL_TX_NPOT_SIZE_W_SHIFT) |
 		       pt->height0);
 	so_data  (so, ps->bcol);
-	so_method(so, nv40->screen->curie, NV40TCL_TEX_SIZE1(unit), 1);
+	so_method(so, nv40->screen->eng3d, NV40TCL_TEX_SIZE1(unit), 1);
 	so_data  (so, (pt->depth0 << NV40TCL_TEX_SIZE1_DEPTH_SHIFT) | txp);
 
 	return so;
@@ -142,7 +142,7 @@ nv40_fragtex_validate(struct nv40_context *nv40)
 		samplers &= ~(1 << unit);
 
 		so = so_new(1, 1, 0);
-		so_method(so, nv40->screen->curie, NV34TCL_TX_ENABLE(unit), 1);
+		so_method(so, nv40->screen->eng3d, NV34TCL_TX_ENABLE(unit), 1);
 		so_data  (so, 0);
 		so_ref(so, &nv40->state.hw[NV40_STATE_FRAGTEX0 + unit]);
 		state->dirty |= (1ULL << (NV40_STATE_FRAGTEX0 + unit));
diff --git a/src/gallium/drivers/nv40/nv40_query.c b/src/gallium/drivers/nv40/nv40_query.c
index 45c5468537..899a8dc0b2 100644
--- a/src/gallium/drivers/nv40/nv40_query.c
+++ b/src/gallium/drivers/nv40/nv40_query.c
@@ -43,7 +43,7 @@ nv40_query_begin(struct pipe_context *pipe, struct pipe_query *pq)
 	struct nv40_query *q = nv40_query(pq);
 	struct nv40_screen *screen = nv40->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *curie = screen->curie;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 
 	assert(q->type == PIPE_QUERY_OCCLUSION_COUNTER);
 
@@ -60,9 +60,9 @@ nv40_query_begin(struct pipe_context *pipe, struct pipe_query *pq)
 		assert(0);
 	nouveau_notifier_reset(nv40->screen->query, q->object->start);
 
-	BEGIN_RING(chan, curie, NV34TCL_QUERY_RESET, 1);
+	BEGIN_RING(chan, eng3d, NV34TCL_QUERY_RESET, 1);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, curie, NV34TCL_QUERY_UNK17CC, 1);
+	BEGIN_RING(chan, eng3d, NV34TCL_QUERY_UNK17CC, 1);
 	OUT_RING  (chan, 1);
 
 	q->ready = FALSE;
@@ -75,9 +75,9 @@ nv40_query_end(struct pipe_context *pipe, struct pipe_query *pq)
 	struct nv40_query *q = nv40_query(pq);
 	struct nv40_screen *screen = nv40->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *curie = screen->curie;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 
-	BEGIN_RING(chan, curie, NV34TCL_QUERY_GET, 1);
+	BEGIN_RING(chan, eng3d, NV34TCL_QUERY_GET, 1);
 	OUT_RING  (chan, (0x01 << NV34TCL_QUERY_GET_UNK24_SHIFT) |
 		   ((q->object->start * 32) << NV34TCL_QUERY_GET_OFFSET_SHIFT));
 	FIRE_RING(chan);
diff --git a/src/gallium/drivers/nv40/nv40_screen.c b/src/gallium/drivers/nv40/nv40_screen.c
index 9c49e2b6ec..3c901c1c53 100644
--- a/src/gallium/drivers/nv40/nv40_screen.c
+++ b/src/gallium/drivers/nv40/nv40_screen.c
@@ -49,7 +49,7 @@ nv40_screen_get_param(struct pipe_screen *pscreen, int param)
 	case NOUVEAU_CAP_HW_VTXBUF:
 		return 1;
 	case NOUVEAU_CAP_HW_IDXBUF:
-		if (screen->curie->grclass == NV40TCL)
+		if (screen->eng3d->grclass == NV40TCL)
 			return 1;
 		return 0;
 	case PIPE_CAP_INDEP_BLEND_ENABLE:
@@ -164,7 +164,7 @@ nv40_screen_destroy(struct pipe_screen *pscreen)
 	nouveau_resource_destroy(&screen->query_heap);
 	nouveau_notifier_free(&screen->query);
 	nouveau_notifier_free(&screen->sync);
-	nouveau_grobj_free(&screen->curie);
+	nouveau_grobj_free(&screen->eng3d);
 	nv04_surface_2d_takedown(&screen->eng2d);
 
 	nouveau_screen_fini(&screen->base);
@@ -179,7 +179,7 @@ nv40_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 	struct nouveau_channel *chan;
 	struct pipe_screen *pscreen;
 	struct nouveau_stateobj *so;
-	unsigned curie_class = 0;
+	unsigned eng3d_class = 0;
 	int ret;
 
 	if (!screen)
@@ -206,23 +206,23 @@ nv40_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 	switch (dev->chipset & 0xf0) {
 	case 0x40:
 		if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
-			curie_class = NV40TCL;
+			eng3d_class = NV40TCL;
 		else
 		if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
-			curie_class = NV44TCL;
+			eng3d_class = NV44TCL;
 		break;
 	case 0x60:
 		if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
-			curie_class = NV44TCL;
+			eng3d_class = NV44TCL;
 		break;
 	}
 
-	if (!curie_class) {
+	if (!eng3d_class) {
 		NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", dev->chipset);
 		return NULL;
 	}
 
-	ret = nouveau_grobj_alloc(chan, 0xbeef3097, curie_class, &screen->curie);
+	ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 	if (ret) {
 		NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 		return FALSE;
@@ -262,52 +262,52 @@ nv40_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 		return NULL;
 	}
 
-	/* Static curie initialisation */
+	/* Static eng3d initialisation */
 	so = so_new(16, 25, 0);
-	so_method(so, screen->curie, NV34TCL_DMA_NOTIFY, 1);
+	so_method(so, screen->eng3d, NV34TCL_DMA_NOTIFY, 1);
 	so_data  (so, screen->sync->handle);
-	so_method(so, screen->curie, NV34TCL_DMA_TEXTURE0, 2);
+	so_method(so, screen->eng3d, NV34TCL_DMA_TEXTURE0, 2);
 	so_data  (so, chan->vram->handle);
 	so_data  (so, chan->gart->handle);
-	so_method(so, screen->curie, NV34TCL_DMA_COLOR1, 1);
+	so_method(so, screen->eng3d, NV34TCL_DMA_COLOR1, 1);
 	so_data  (so, chan->vram->handle);
-	so_method(so, screen->curie, NV34TCL_DMA_COLOR0, 2);
+	so_method(so, screen->eng3d, NV34TCL_DMA_COLOR0, 2);
 	so_data  (so, chan->vram->handle);
 	so_data  (so, chan->vram->handle);
-	so_method(so, screen->curie, NV34TCL_DMA_VTXBUF0, 2);
+	so_method(so, screen->eng3d, NV34TCL_DMA_VTXBUF0, 2);
 	so_data  (so, chan->vram->handle);
 	so_data  (so, chan->gart->handle);
-	so_method(so, screen->curie, NV34TCL_DMA_FENCE, 2);
+	so_method(so, screen->eng3d, NV34TCL_DMA_FENCE, 2);
 	so_data  (so, 0);
 	so_data  (so, screen->query->handle);
-	so_method(so, screen->curie, NV34TCL_DMA_IN_MEMORY7, 2);
+	so_method(so, screen->eng3d, NV34TCL_DMA_IN_MEMORY7, 2);
 	so_data  (so, chan->vram->handle);
 	so_data  (so, chan->vram->handle);
-	so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
+	so_method(so, screen->eng3d, NV40TCL_DMA_COLOR2, 2);
 	so_data  (so, chan->vram->handle);
 	so_data  (so, chan->vram->handle);
 
-	so_method(so, screen->curie, 0x1ea4, 3);
+	so_method(so, screen->eng3d, 0x1ea4, 3);
 	so_data  (so, 0x00000010);
 	so_data  (so, 0x01000100);
 	so_data  (so, 0xff800006);
 
 	/* vtxprog output routing */
-	so_method(so, screen->curie, 0x1fc4, 1);
+	so_method(so, screen->eng3d, 0x1fc4, 1);
 	so_data  (so, 0x06144321);
-	so_method(so, screen->curie, 0x1fc8, 2);
+	so_method(so, screen->eng3d, 0x1fc8, 2);
 	so_data  (so, 0xedcba987);
 	so_data  (so, 0x00000021);
-	so_method(so, screen->curie, 0x1fd0, 1);
+	so_method(so, screen->eng3d, 0x1fd0, 1);
 	so_data  (so, 0x00171615);
-	so_method(so, screen->curie, 0x1fd4, 1);
+	so_method(so, screen->eng3d, 0x1fd4, 1);
 	so_data  (so, 0x001b1a19);
 
-	so_method(so, screen->curie, 0x1ef8, 1);
+	so_method(so, screen->eng3d, 0x1ef8, 1);
 	so_data  (so, 0x0020ffff);
-	so_method(so, screen->curie, 0x1d64, 1);
+	so_method(so, screen->eng3d, 0x1d64, 1);
 	so_data  (so, 0x00d30000);
-	so_method(so, screen->curie, 0x1e94, 1);
+	so_method(so, screen->eng3d, 0x1e94, 1);
 	so_data  (so, 0x00000001);
 
 	so_emit(chan, so);
diff --git a/src/gallium/drivers/nv40/nv40_screen.h b/src/gallium/drivers/nv40/nv40_screen.h
index 2765ab764a..ad0ee63da6 100644
--- a/src/gallium/drivers/nv40/nv40_screen.h
+++ b/src/gallium/drivers/nv40/nv40_screen.h
@@ -13,7 +13,7 @@ struct nv40_screen {
 
 	/* HW graphics objects */
 	struct nv04_surface_2d *eng2d;
-	struct nouveau_grobj *curie;
+	struct nouveau_grobj *eng3d;
 	struct nouveau_notifier *sync;
 
 	/* Query object resources */
diff --git a/src/gallium/drivers/nv40/nv40_state.c b/src/gallium/drivers/nv40/nv40_state.c
index 3db000a219..e8076e059b 100644
--- a/src/gallium/drivers/nv40/nv40_state.c
+++ b/src/gallium/drivers/nv40/nv40_state.c
@@ -14,41 +14,41 @@ nv40_blend_state_create(struct pipe_context *pipe,
 			const struct pipe_blend_state *cso)
 {
 	struct nv40_context *nv40 = nv40_context(pipe);
-	struct nouveau_grobj *curie = nv40->screen->curie;
+	struct nouveau_grobj *eng3d = nv40->screen->eng3d;
 	struct nv40_blend_state *bso = CALLOC(1, sizeof(*bso));
 	struct nouveau_stateobj *so = so_new(5, 8, 0);
 
 	if (cso->rt[0].blend_enable) {
-		so_method(so, curie, NV34TCL_BLEND_FUNC_ENABLE, 3);
+		so_method(so, eng3d, NV34TCL_BLEND_FUNC_ENABLE, 3);
 		so_data  (so, 1);
 		so_data  (so, (nvgl_blend_func(cso->rt[0].alpha_src_factor) << 16) |
 			       nvgl_blend_func(cso->rt[0].rgb_src_factor));
 		so_data  (so, nvgl_blend_func(cso->rt[0].alpha_dst_factor) << 16 |
 			      nvgl_blend_func(cso->rt[0].rgb_dst_factor));
-		so_method(so, curie, NV40TCL_BLEND_EQUATION, 1);
+		so_method(so, eng3d, NV40TCL_BLEND_EQUATION, 1);
 		so_data  (so, nvgl_blend_eqn(cso->rt[0].alpha_func) << 16 |
 			      nvgl_blend_eqn(cso->rt[0].rgb_func));
 	} else {
-		so_method(so, curie, NV34TCL_BLEND_FUNC_ENABLE, 1);
+		so_method(so, eng3d, NV34TCL_BLEND_FUNC_ENABLE, 1);
 		so_data  (so, 0);
 	}
 
-	so_method(so, curie, NV34TCL_COLOR_MASK, 1);
+	so_method(so, eng3d, NV34TCL_COLOR_MASK, 1);
 	so_data  (so, (((cso->rt[0].colormask & PIPE_MASK_A) ? (0x01 << 24) : 0) |
 		       ((cso->rt[0].colormask & PIPE_MASK_R) ? (0x01 << 16) : 0) |
 		       ((cso->rt[0].colormask & PIPE_MASK_G) ? (0x01 <<  8) : 0) |
 		       ((cso->rt[0].colormask & PIPE_MASK_B) ? (0x01 <<  0) : 0)));
 
 	if (cso->logicop_enable) {
-		so_method(so, curie, NV34TCL_COLOR_LOGIC_OP_ENABLE, 2);
+		so_method(so, eng3d, NV34TCL_COLOR_LOGIC_OP_ENABLE, 2);
 		so_data  (so, 1);
 		so_data  (so, nvgl_logicop_func(cso->logicop_func));
 	} else {
-		so_method(so, curie, NV34TCL_COLOR_LOGIC_OP_ENABLE, 1);
+		so_method(so, eng3d, NV34TCL_COLOR_LOGIC_OP_ENABLE, 1);
 		so_data  (so, 0);
 	}
 
-	so_method(so, curie, NV34TCL_DITHER_ENABLE, 1);
+	so_method(so, eng3d, NV34TCL_DITHER_ENABLE, 1);
 	so_data  (so, cso->dither ? 1 : 0);
 
 	so_ref(so, &bso->so);
@@ -311,7 +311,7 @@ nv40_rasterizer_state_create(struct pipe_context *pipe,
 	struct nv40_context *nv40 = nv40_context(pipe);
 	struct nv40_rasterizer_state *rsso = CALLOC(1, sizeof(*rsso));
 	struct nouveau_stateobj *so = so_new(9, 19, 0);
-	struct nouveau_grobj *curie = nv40->screen->curie;
+	struct nouveau_grobj *eng3d = nv40->screen->eng3d;
 
 	/*XXX: ignored:
 	 * 	light_twoside
@@ -319,22 +319,22 @@ nv40_rasterizer_state_create(struct pipe_context *pipe,
 	 * 	multisample
 	 */
 
-	so_method(so, curie, NV34TCL_SHADE_MODEL, 1);
+	so_method(so, eng3d, NV34TCL_SHADE_MODEL, 1);
 	so_data  (so, cso->flatshade ? NV34TCL_SHADE_MODEL_FLAT :
 				       NV34TCL_SHADE_MODEL_SMOOTH);
 
-	so_method(so, curie, NV34TCL_LINE_WIDTH, 2);
+	so_method(so, eng3d, NV34TCL_LINE_WIDTH, 2);
 	so_data  (so, (unsigned char)(cso->line_width * 8.0) & 0xff);
 	so_data  (so, cso->line_smooth ? 1 : 0);
-	so_method(so, curie, NV34TCL_LINE_STIPPLE_ENABLE, 2);
+	so_method(so, eng3d, NV34TCL_LINE_STIPPLE_ENABLE, 2);
 	so_data  (so, cso->line_stipple_enable ? 1 : 0);
 	so_data  (so, (cso->line_stipple_pattern << 16) |
 		       cso->line_stipple_factor);
 
-	so_method(so, curie, NV34TCL_POINT_SIZE, 1);
+	so_method(so, eng3d, NV34TCL_POINT_SIZE, 1);
 	so_data  (so, fui(cso->point_size));
 
-	so_method(so, curie, NV34TCL_POLYGON_MODE_FRONT, 6);
+	so_method(so, eng3d, NV34TCL_POLYGON_MODE_FRONT, 6);
 	if (cso->front_winding == PIPE_WINDING_CCW) {
 		so_data(so, nvgl_polygon_mode(cso->fill_ccw));
 		so_data(so, nvgl_polygon_mode(cso->fill_cw));
@@ -375,10 +375,10 @@ nv40_rasterizer_state_create(struct pipe_context *pipe,
 	so_data(so, cso->poly_smooth ? 1 : 0);
 	so_data(so, (cso->cull_mode != PIPE_WINDING_NONE) ? 1 : 0);
 
-	so_method(so, curie, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
+	so_method(so, eng3d, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
 	so_data  (so, cso->poly_stipple_enable ? 1 : 0);
 
-	so_method(so, curie, NV34TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
+	so_method(so, eng3d, NV34TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
 	if ((cso->offset_cw && cso->fill_cw == PIPE_POLYGON_MODE_POINT) ||
 	    (cso->offset_ccw && cso->fill_ccw == PIPE_POLYGON_MODE_POINT))
 		so_data(so, 1);
@@ -395,12 +395,12 @@ nv40_rasterizer_state_create(struct pipe_context *pipe,
 	else
 		so_data(so, 0);
 	if (cso->offset_cw || cso->offset_ccw) {
-		so_method(so, curie, NV34TCL_POLYGON_OFFSET_FACTOR, 2);
+		so_method(so, eng3d, NV34TCL_POLYGON_OFFSET_FACTOR, 2);
 		so_data  (so, fui(cso->offset_scale));
 		so_data  (so, fui(cso->offset_units * 2));
 	}
 
-	so_method(so, curie, NV34TCL_POINT_SPRITE, 1);
+	so_method(so, eng3d, NV34TCL_POINT_SPRITE, 1);
 	if (cso->point_quad_rasterization) {
 		unsigned psctl = (1 << 0), i;
 
@@ -446,45 +446,45 @@ nv40_depth_stencil_alpha_state_create(struct pipe_context *pipe,
 	struct nv40_context *nv40 = nv40_context(pipe);
 	struct nv40_zsa_state *zsaso = CALLOC(1, sizeof(*zsaso));
 	struct nouveau_stateobj *so = so_new(6, 20, 0);
-	struct nouveau_grobj *curie = nv40->screen->curie;
+	struct nouveau_grobj *eng3d = nv40->screen->eng3d;
 
-	so_method(so, curie, NV34TCL_DEPTH_FUNC, 3);
+	so_method(so, eng3d, NV34TCL_DEPTH_FUNC, 3);
 	so_data  (so, nvgl_comparison_op(cso->depth.func));
 	so_data  (so, cso->depth.writemask ? 1 : 0);
 	so_data  (so, cso->depth.enabled ? 1 : 0);
 
-	so_method(so, curie, NV34TCL_ALPHA_FUNC_ENABLE, 3);
+	so_method(so, eng3d, NV34TCL_ALPHA_FUNC_ENABLE, 3);
 	so_data  (so, cso->alpha.enabled ? 1 : 0);
 	so_data  (so, nvgl_comparison_op(cso->alpha.func));
 	so_data  (so, float_to_ubyte(cso->alpha.ref_value));
 
 	if (cso->stencil[0].enabled) {
-		so_method(so, curie, NV34TCL_STENCIL_FRONT_ENABLE, 3);
+		so_method(so, eng3d, NV34TCL_STENCIL_FRONT_ENABLE, 3);
 		so_data  (so, cso->stencil[0].enabled ? 1 : 0);
 		so_data  (so, cso->stencil[0].writemask);
 		so_data  (so, nvgl_comparison_op(cso->stencil[0].func));
-		so_method(so, curie, NV34TCL_STENCIL_FRONT_FUNC_MASK, 4);
+		so_method(so, eng3d, NV34TCL_STENCIL_FRONT_FUNC_MASK, 4);
 		so_data  (so, cso->stencil[0].valuemask);
 		so_data  (so, nvgl_stencil_op(cso->stencil[0].fail_op));
 		so_data  (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
 		so_data  (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
 	} else {
-		so_method(so, curie, NV34TCL_STENCIL_FRONT_ENABLE, 1);
+		so_method(so, eng3d, NV34TCL_STENCIL_FRONT_ENABLE, 1);
 		so_data  (so, 0);
 	}
 
 	if (cso->stencil[1].enabled) {
-		so_method(so, curie, NV34TCL_STENCIL_BACK_ENABLE, 3);
+		so_method(so, eng3d, NV34TCL_STENCIL_BACK_ENABLE, 3);
 		so_data  (so, cso->stencil[1].enabled ? 1 : 0);
 		so_data  (so, cso->stencil[1].writemask);
 		so_data  (so, nvgl_comparison_op(cso->stencil[1].func));
-		so_method(so, curie, NV34TCL_STENCIL_BACK_FUNC_MASK, 4);
+		so_method(so, eng3d, NV34TCL_STENCIL_BACK_FUNC_MASK, 4);
 		so_data  (so, cso->stencil[1].valuemask);
 		so_data  (so, nvgl_stencil_op(cso->stencil[1].fail_op));
 		so_data  (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
 		so_data  (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
 	} else {
-		so_method(so, curie, NV34TCL_STENCIL_BACK_ENABLE, 1);
+		so_method(so, eng3d, NV34TCL_STENCIL_BACK_ENABLE, 1);
 		so_data  (so, 0);
 	}
 
diff --git a/src/gallium/drivers/nv40/nv40_state_blend.c b/src/gallium/drivers/nv40/nv40_state_blend.c
index 9da13123ab..83202ec23c 100644
--- a/src/gallium/drivers/nv40/nv40_state_blend.c
+++ b/src/gallium/drivers/nv40/nv40_state_blend.c
@@ -21,7 +21,7 @@ nv40_state_blend_colour_validate(struct nv40_context *nv40)
 	struct nouveau_stateobj *so = so_new(1, 1, 0);
 	struct pipe_blend_color *bcol = &nv40->blend_colour;
 
-	so_method(so, nv40->screen->curie, NV34TCL_BLEND_COLOR, 1);
+	so_method(so, nv40->screen->eng3d, NV34TCL_BLEND_COLOR, 1);
 	so_data  (so, ((float_to_ubyte(bcol->color[3]) << 24) |
 		       (float_to_ubyte(bcol->color[0]) << 16) |
 		       (float_to_ubyte(bcol->color[1]) <<  8) |
diff --git a/src/gallium/drivers/nv40/nv40_state_emit.c b/src/gallium/drivers/nv40/nv40_state_emit.c
index 297d71f4fa..6ad7a8d4fd 100644
--- a/src/gallium/drivers/nv40/nv40_state_emit.c
+++ b/src/gallium/drivers/nv40/nv40_state_emit.c
@@ -59,7 +59,7 @@ nv40_state_emit(struct nv40_context *nv40)
 	struct nv40_state *state = &nv40->state;
 	struct nv40_screen *screen = nv40->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *curie = screen->curie;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 	unsigned i;
 	uint64_t states;
 
@@ -85,9 +85,9 @@ nv40_state_emit(struct nv40_context *nv40)
 
 	if (state->dirty & ((1ULL << NV40_STATE_FRAGPROG) |
 			    (1ULL << NV40_STATE_FRAGTEX0))) {
-		BEGIN_RING(chan, curie, NV40TCL_TEX_CACHE_CTL, 1);
+		BEGIN_RING(chan, eng3d, NV40TCL_TEX_CACHE_CTL, 1);
 		OUT_RING  (chan, 2);
-		BEGIN_RING(chan, curie, NV40TCL_TEX_CACHE_CTL, 1);
+		BEGIN_RING(chan, eng3d, NV40TCL_TEX_CACHE_CTL, 1);
 		OUT_RING  (chan, 1);
 	}
 
diff --git a/src/gallium/drivers/nv40/nv40_state_fb.c b/src/gallium/drivers/nv40/nv40_state_fb.c
index 93e91b9e3b..207b70923e 100644
--- a/src/gallium/drivers/nv40/nv40_state_fb.c
+++ b/src/gallium/drivers/nv40/nv40_state_fb.c
@@ -14,7 +14,7 @@ static boolean
 nv40_state_framebuffer_validate(struct nv40_context *nv40)
 {
 	struct nouveau_channel *chan = nv40->screen->base.channel;
-	struct nouveau_grobj *curie = nv40->screen->curie;
+	struct nouveau_grobj *eng3d = nv40->screen->eng3d;
 	struct pipe_framebuffer_state *fb = &nv40->framebuffer;
 	struct nv04_surface *rt[4], *zeta;
 	uint32_t rt_enable, rt_format;
@@ -85,11 +85,11 @@ nv40_state_framebuffer_validate(struct nv40_context *nv40)
 	}
 
 	if (rt_enable & NV40TCL_RT_ENABLE_COLOR0) {
-		so_method(so, curie, NV34TCL_DMA_COLOR0, 1);
+		so_method(so, eng3d, NV34TCL_DMA_COLOR0, 1);
 		so_reloc (so, nv40_surface_buffer(&rt[0]->base), 0,
 			      rt_flags | NOUVEAU_BO_OR,
 			      chan->vram->handle, chan->gart->handle);
-		so_method(so, curie, NV34TCL_COLOR0_PITCH, 2);
+		so_method(so, eng3d, NV34TCL_COLOR0_PITCH, 2);
 		so_data  (so, rt[0]->pitch);
 		so_reloc (so, nv40_surface_buffer(&rt[0]->base),
 			      rt[0]->base.offset, rt_flags | NOUVEAU_BO_LOW,
@@ -97,11 +97,11 @@ nv40_state_framebuffer_validate(struct nv40_context *nv40)
 	}
 
 	if (rt_enable & NV40TCL_RT_ENABLE_COLOR1) {
-		so_method(so, curie, NV34TCL_DMA_COLOR1, 1);
+		so_method(so, eng3d, NV34TCL_DMA_COLOR1, 1);
 		so_reloc (so, nv40_surface_buffer(&rt[1]->base), 0,
 			      rt_flags | NOUVEAU_BO_OR,
 			      chan->vram->handle, chan->gart->handle);
-		so_method(so, curie, NV34TCL_COLOR1_OFFSET, 2);
+		so_method(so, eng3d, NV34TCL_COLOR1_OFFSET, 2);
 		so_reloc (so, nv40_surface_buffer(&rt[1]->base),
 			      rt[1]->base.offset, rt_flags | NOUVEAU_BO_LOW,
 			      0, 0);
@@ -109,56 +109,56 @@ nv40_state_framebuffer_validate(struct nv40_context *nv40)
 	}
 
 	if (rt_enable & NV40TCL_RT_ENABLE_COLOR2) {
-		so_method(so, curie, NV40TCL_DMA_COLOR2, 1);
+		so_method(so, eng3d, NV40TCL_DMA_COLOR2, 1);
 		so_reloc (so, nv40_surface_buffer(&rt[2]->base), 0,
 			      rt_flags | NOUVEAU_BO_OR,
 			      chan->vram->handle, chan->gart->handle);
-		so_method(so, curie, NV40TCL_COLOR2_OFFSET, 1);
+		so_method(so, eng3d, NV40TCL_COLOR2_OFFSET, 1);
 		so_reloc (so, nv40_surface_buffer(&rt[2]->base),
 			      rt[2]->base.offset, rt_flags | NOUVEAU_BO_LOW,
 			      0, 0);
-		so_method(so, curie, NV40TCL_COLOR2_PITCH, 1);
+		so_method(so, eng3d, NV40TCL_COLOR2_PITCH, 1);
 		so_data  (so, rt[2]->pitch);
 	}
 
 	if (rt_enable & NV40TCL_RT_ENABLE_COLOR3) {
-		so_method(so, curie, NV40TCL_DMA_COLOR3, 1);
+		so_method(so, eng3d, NV40TCL_DMA_COLOR3, 1);
 		so_reloc (so, nv40_surface_buffer(&rt[3]->base), 0,
 			      rt_flags | NOUVEAU_BO_OR,
 			      chan->vram->handle, chan->gart->handle);
-		so_method(so, curie, NV40TCL_COLOR3_OFFSET, 1);
+		so_method(so, eng3d, NV40TCL_COLOR3_OFFSET, 1);
 		so_reloc (so, nv40_surface_buffer(&rt[3]->base),
 			      rt[3]->base.offset, rt_flags | NOUVEAU_BO_LOW,
 			      0, 0);
-		so_method(so, curie, NV40TCL_COLOR3_PITCH, 1);
+		so_method(so, eng3d, NV40TCL_COLOR3_PITCH, 1);
 		so_data  (so, rt[3]->pitch);
 	}
 
 	if (zeta_format) {
-		so_method(so, curie, NV34TCL_DMA_ZETA, 1);
+		so_method(so, eng3d, NV34TCL_DMA_ZETA, 1);
 		so_reloc (so, nv40_surface_buffer(&zeta->base), 0,
 			      rt_flags | NOUVEAU_BO_OR,
 			      chan->vram->handle, chan->gart->handle);
-		so_method(so, curie, NV34TCL_ZETA_OFFSET, 1);
+		so_method(so, eng3d, NV34TCL_ZETA_OFFSET, 1);
 		so_reloc (so, nv40_surface_buffer(&zeta->base),
 			      zeta->base.offset, rt_flags | NOUVEAU_BO_LOW, 0, 0);
-		so_method(so, curie, NV40TCL_ZETA_PITCH, 1);
+		so_method(so, eng3d, NV40TCL_ZETA_PITCH, 1);
 		so_data  (so, zeta->pitch);
 	}
 
-	so_method(so, curie, NV40TCL_RT_ENABLE, 1);
+	so_method(so, eng3d, NV40TCL_RT_ENABLE, 1);
 	so_data  (so, rt_enable);
-	so_method(so, curie, NV34TCL_RT_HORIZ, 3);
+	so_method(so, eng3d, NV34TCL_RT_HORIZ, 3);
 	so_data  (so, (w << 16) | 0);
 	so_data  (so, (h << 16) | 0);
 	so_data  (so, rt_format);
-	so_method(so, curie, NV34TCL_VIEWPORT_HORIZ, 2);
+	so_method(so, eng3d, NV34TCL_VIEWPORT_HORIZ, 2);
 	so_data  (so, (w << 16) | 0);
 	so_data  (so, (h << 16) | 0);
-	so_method(so, curie, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2);
+	so_method(so, eng3d, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2);
 	so_data  (so, ((w - 1) << 16) | 0);
 	so_data  (so, ((h - 1) << 16) | 0);
-	so_method(so, curie, 0x1d88, 1);
+	so_method(so, eng3d, 0x1d88, 1);
 	so_data  (so, (1 << 12) | h);
 
 	so_ref(so, &nv40->state.hw[NV40_STATE_FB]);
diff --git a/src/gallium/drivers/nv40/nv40_state_scissor.c b/src/gallium/drivers/nv40/nv40_state_scissor.c
index 91bff4849c..dcb068d059 100644
--- a/src/gallium/drivers/nv40/nv40_state_scissor.c
+++ b/src/gallium/drivers/nv40/nv40_state_scissor.c
@@ -13,7 +13,7 @@ nv40_state_scissor_validate(struct nv40_context *nv40)
 	nv40->state.scissor_enabled = rast->scissor;
 
 	so = so_new(1, 2, 0);
-	so_method(so, nv40->screen->curie, NV34TCL_SCISSOR_HORIZ, 2);
+	so_method(so, nv40->screen->eng3d, NV34TCL_SCISSOR_HORIZ, 2);
 	if (nv40->state.scissor_enabled) {
 		so_data  (so, ((s->maxx - s->minx) << 16) | s->minx);
 		so_data  (so, ((s->maxy - s->miny) << 16) | s->miny);
diff --git a/src/gallium/drivers/nv40/nv40_state_stipple.c b/src/gallium/drivers/nv40/nv40_state_stipple.c
index ed8643b9c1..4514618772 100644
--- a/src/gallium/drivers/nv40/nv40_state_stipple.c
+++ b/src/gallium/drivers/nv40/nv40_state_stipple.c
@@ -4,7 +4,7 @@ static boolean
 nv40_state_stipple_validate(struct nv40_context *nv40)
 {
 	struct pipe_rasterizer_state *rast = &nv40->rasterizer->pipe;
-	struct nouveau_grobj *curie = nv40->screen->curie;
+	struct nouveau_grobj *eng3d = nv40->screen->eng3d;
 	struct nouveau_stateobj *so;
 
 	if (nv40->state.hw[NV40_STATE_STIPPLE] &&
@@ -15,14 +15,14 @@ nv40_state_stipple_validate(struct nv40_context *nv40)
 		unsigned i;
 
 		so = so_new(2, 33, 0);
-		so_method(so, curie, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
+		so_method(so, eng3d, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
 		so_data  (so, 1);
-		so_method(so, curie, NV34TCL_POLYGON_STIPPLE_PATTERN(0), 32);
+		so_method(so, eng3d, NV34TCL_POLYGON_STIPPLE_PATTERN(0), 32);
 		for (i = 0; i < 32; i++)
 			so_data(so, nv40->stipple[i]);
 	} else {
 		so = so_new(1, 1, 0);
-		so_method(so, curie, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
+		so_method(so, eng3d, NV34TCL_POLYGON_STIPPLE_ENABLE, 1);
 		so_data  (so, 0);
 	}
 
diff --git a/src/gallium/drivers/nv40/nv40_state_viewport.c b/src/gallium/drivers/nv40/nv40_state_viewport.c
index 3a5ea0e480..43cf6e5a0a 100644
--- a/src/gallium/drivers/nv40/nv40_state_viewport.c
+++ b/src/gallium/drivers/nv40/nv40_state_viewport.c
@@ -11,7 +11,7 @@ nv40_state_viewport_validate(struct nv40_context *nv40)
 		return FALSE;
 
 	so = so_new(2, 9, 0);
-	so_method(so, nv40->screen->curie,
+	so_method(so, nv40->screen->eng3d,
 		  NV34TCL_VIEWPORT_TRANSLATE_X, 8);
 	so_data  (so, fui(vpt->translate[0]));
 	so_data  (so, fui(vpt->translate[1]));
@@ -21,7 +21,7 @@ nv40_state_viewport_validate(struct nv40_context *nv40)
 	so_data  (so, fui(vpt->scale[1]));
 	so_data  (so, fui(vpt->scale[2]));
 	so_data  (so, fui(vpt->scale[3]));
-	so_method(so, nv40->screen->curie, 0x1d78, 1);
+	so_method(so, nv40->screen->eng3d, 0x1d78, 1);
 	so_data  (so, 1);
 
 	so_ref(so, &nv40->state.hw[NV40_STATE_VIEWPORT]);
diff --git a/src/gallium/drivers/nv40/nv40_state_zsa.c b/src/gallium/drivers/nv40/nv40_state_zsa.c
index bf68c60ace..cb56948a1b 100644
--- a/src/gallium/drivers/nv40/nv40_state_zsa.c
+++ b/src/gallium/drivers/nv40/nv40_state_zsa.c
@@ -22,9 +22,9 @@ nv40_state_sr_validate(struct nv40_context *nv40)
 	struct nouveau_stateobj *so = so_new(2, 2, 0);
 	struct pipe_stencil_ref *sr = &nv40->stencil_ref;
 
-	so_method(so, nv40->screen->curie, NV34TCL_STENCIL_FRONT_FUNC_REF, 1);
+	so_method(so, nv40->screen->eng3d, NV34TCL_STENCIL_FRONT_FUNC_REF, 1);
 	so_data  (so, sr->ref_value[0]);
-	so_method(so, nv40->screen->curie, NV34TCL_STENCIL_BACK_FUNC_REF, 1);
+	so_method(so, nv40->screen->eng3d, NV34TCL_STENCIL_BACK_FUNC_REF, 1);
 	so_data  (so, sr->ref_value[1]);
 
 	so_ref(so, &nv40->state.hw[NV40_STATE_SR]);
diff --git a/src/gallium/drivers/nv40/nv40_vbo.c b/src/gallium/drivers/nv40/nv40_vbo.c
index a2f06ead86..b77c9e924b 100644
--- a/src/gallium/drivers/nv40/nv40_vbo.c
+++ b/src/gallium/drivers/nv40/nv40_vbo.c
@@ -111,7 +111,7 @@ nv40_vbo_static_attrib(struct nv40_context *nv40, struct nouveau_stateobj *so,
 		       struct pipe_vertex_buffer *vb)
 {
 	struct pipe_screen *pscreen = nv40->pipe.screen;
-	struct nouveau_grobj *curie = nv40->screen->curie;
+	struct nouveau_grobj *eng3d = nv40->screen->eng3d;
 	unsigned type, ncomp;
 	void *map;
 
@@ -128,25 +128,25 @@ nv40_vbo_static_attrib(struct nv40_context *nv40, struct nouveau_stateobj *so,
 
 		switch (ncomp) {
 		case 4:
-			so_method(so, curie, NV34TCL_VTX_ATTR_4F_X(attrib), 4);
+			so_method(so, eng3d, NV34TCL_VTX_ATTR_4F_X(attrib), 4);
 			so_data  (so, fui(v[0]));
 			so_data  (so, fui(v[1]));
 			so_data  (so, fui(v[2]));
 			so_data  (so, fui(v[3]));
 			break;
 		case 3:
-			so_method(so, curie, NV34TCL_VTX_ATTR_3F_X(attrib), 3);
+			so_method(so, eng3d, NV34TCL_VTX_ATTR_3F_X(attrib), 3);
 			so_data  (so, fui(v[0]));
 			so_data  (so, fui(v[1]));
 			so_data  (so, fui(v[2]));
 			break;
 		case 2:
-			so_method(so, curie, NV34TCL_VTX_ATTR_2F_X(attrib), 2);
+			so_method(so, eng3d, NV34TCL_VTX_ATTR_2F_X(attrib), 2);
 			so_data  (so, fui(v[0]));
 			so_data  (so, fui(v[1]));
 			break;
 		case 1:
-			so_method(so, curie, NV34TCL_VTX_ATTR_1F(attrib), 1);
+			so_method(so, eng3d, NV34TCL_VTX_ATTR_1F(attrib), 1);
 			so_data  (so, fui(v[0]));
 			break;
 		default:
@@ -172,7 +172,7 @@ nv40_draw_arrays(struct pipe_context *pipe,
 	struct nv40_context *nv40 = nv40_context(pipe);
 	struct nv40_screen *screen = nv40->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *curie = screen->curie;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 	unsigned restart;
 
 	nv40_vbo_set_idxbuf(nv40, NULL, 0);
@@ -194,12 +194,12 @@ nv40_draw_arrays(struct pipe_context *pipe,
 			continue;
 		}
 
-		BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, nvgl_primitive(mode));
 
 		nr = (vc & 0xff);
 		if (nr) {
-			BEGIN_RING(chan, curie, NV34TCL_VB_VERTEX_BATCH, 1);
+			BEGIN_RING(chan, eng3d, NV34TCL_VB_VERTEX_BATCH, 1);
 			OUT_RING  (chan, ((nr - 1) << 24) | start);
 			start += nr;
 		}
@@ -210,14 +210,14 @@ nv40_draw_arrays(struct pipe_context *pipe,
 
 			nr -= push;
 
-			BEGIN_RING_NI(chan, curie, NV34TCL_VB_VERTEX_BATCH, push);
+			BEGIN_RING_NI(chan, eng3d, NV34TCL_VB_VERTEX_BATCH, push);
 			while (push--) {
 				OUT_RING(chan, ((0x100 - 1) << 24) | start);
 				start += 0x100;
 			}
 		}
 
-		BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, 0);
 
 		count -= vc;
@@ -233,7 +233,7 @@ nv40_draw_elements_u08(struct nv40_context *nv40, void *ib,
 {
 	struct nv40_screen *screen = nv40->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *curie = screen->curie;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 
 	while (count) {
 		uint8_t *elts = (uint8_t *)ib + start;
@@ -249,11 +249,11 @@ nv40_draw_elements_u08(struct nv40_context *nv40, void *ib,
 		}
 		count -= vc;
 
-		BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, nvgl_primitive(mode));
 
 		if (vc & 1) {
-			BEGIN_RING(chan, curie, NV34TCL_VB_ELEMENT_U32, 1);
+			BEGIN_RING(chan, eng3d, NV34TCL_VB_ELEMENT_U32, 1);
 			OUT_RING  (chan, elts[0]);
 			elts++; vc--;
 		}
@@ -263,7 +263,7 @@ nv40_draw_elements_u08(struct nv40_context *nv40, void *ib,
 
 			push = MIN2(vc, 2047 * 2);
 
-			BEGIN_RING_NI(chan, curie, NV34TCL_VB_ELEMENT_U16, push >> 1);
+			BEGIN_RING_NI(chan, eng3d, NV34TCL_VB_ELEMENT_U16, push >> 1);
 			for (i = 0; i < push; i+=2)
 				OUT_RING(chan, (elts[i+1] << 16) | elts[i]);
 
@@ -271,7 +271,7 @@ nv40_draw_elements_u08(struct nv40_context *nv40, void *ib,
 			elts += push;
 		}
 
-		BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, 0);
 
 		start = restart;
@@ -284,7 +284,7 @@ nv40_draw_elements_u16(struct nv40_context *nv40, void *ib,
 {
 	struct nv40_screen *screen = nv40->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *curie = screen->curie;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 
 	while (count) {
 		uint16_t *elts = (uint16_t *)ib + start;
@@ -300,11 +300,11 @@ nv40_draw_elements_u16(struct nv40_context *nv40, void *ib,
 		}
 		count -= vc;
 
-		BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, nvgl_primitive(mode));
 
 		if (vc & 1) {
-			BEGIN_RING(chan, curie, NV34TCL_VB_ELEMENT_U32, 1);
+			BEGIN_RING(chan, eng3d, NV34TCL_VB_ELEMENT_U32, 1);
 			OUT_RING  (chan, elts[0]);
 			elts++; vc--;
 		}
@@ -314,7 +314,7 @@ nv40_draw_elements_u16(struct nv40_context *nv40, void *ib,
 
 			push = MIN2(vc, 2047 * 2);
 
-			BEGIN_RING_NI(chan, curie, NV34TCL_VB_ELEMENT_U16, push >> 1);
+			BEGIN_RING_NI(chan, eng3d, NV34TCL_VB_ELEMENT_U16, push >> 1);
 			for (i = 0; i < push; i+=2)
 				OUT_RING(chan, (elts[i+1] << 16) | elts[i]);
 
@@ -322,7 +322,7 @@ nv40_draw_elements_u16(struct nv40_context *nv40, void *ib,
 			elts += push;
 		}
 
-		BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, 0);
 
 		start = restart;
@@ -335,7 +335,7 @@ nv40_draw_elements_u32(struct nv40_context *nv40, void *ib,
 {
 	struct nv40_screen *screen = nv40->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *curie = screen->curie;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 
 	while (count) {
 		uint32_t *elts = (uint32_t *)ib + start;
@@ -351,20 +351,20 @@ nv40_draw_elements_u32(struct nv40_context *nv40, void *ib,
 		}
 		count -= vc;
 
-		BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, nvgl_primitive(mode));
 
 		while (vc) {
 			push = MIN2(vc, 2047);
 
-			BEGIN_RING_NI(chan, curie, NV34TCL_VB_ELEMENT_U32, push);
+			BEGIN_RING_NI(chan, eng3d, NV34TCL_VB_ELEMENT_U32, push);
 			OUT_RINGp    (chan, elts, push);
 
 			vc -= push;
 			elts += push;
 		}
 
-		BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, 0);
 
 		start = restart;
@@ -411,7 +411,7 @@ nv40_draw_elements_vbo(struct pipe_context *pipe,
 	struct nv40_context *nv40 = nv40_context(pipe);
 	struct nv40_screen *screen = nv40->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *curie = screen->curie;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 	unsigned restart;
 
 	while (count) {
@@ -426,12 +426,12 @@ nv40_draw_elements_vbo(struct pipe_context *pipe,
 			continue;
 		}
 
-		BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, nvgl_primitive(mode));
 
 		nr = (vc & 0xff);
 		if (nr) {
-			BEGIN_RING(chan, curie, NV34TCL_VB_INDEX_BATCH, 1);
+			BEGIN_RING(chan, eng3d, NV34TCL_VB_INDEX_BATCH, 1);
 			OUT_RING  (chan, ((nr - 1) << 24) | start);
 			start += nr;
 		}
@@ -442,14 +442,14 @@ nv40_draw_elements_vbo(struct pipe_context *pipe,
 
 			nr -= push;
 
-			BEGIN_RING_NI(chan, curie, NV34TCL_VB_INDEX_BATCH, push);
+			BEGIN_RING_NI(chan, eng3d, NV34TCL_VB_INDEX_BATCH, push);
 			while (push--) {
 				OUT_RING(chan, ((0x100 - 1) << 24) | start);
 				start += 0x100;
 			}
 		}
 
-		BEGIN_RING(chan, curie, NV34TCL_VERTEX_BEGIN_END, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VERTEX_BEGIN_END, 1);
 		OUT_RING  (chan, 0);
 
 		count -= vc;
@@ -486,16 +486,16 @@ static boolean
 nv40_vbo_validate(struct nv40_context *nv40)
 {
 	struct nouveau_stateobj *vtxbuf, *vtxfmt, *sattr = NULL;
-	struct nouveau_grobj *curie = nv40->screen->curie;
+	struct nouveau_grobj *eng3d = nv40->screen->eng3d;
 	struct pipe_buffer *ib = nv40->idxbuf;
 	unsigned ib_format = nv40->idxbuf_format;
 	unsigned vb_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
 	int hw;
 
 	vtxbuf = so_new(3, 17, 18);
-	so_method(vtxbuf, curie, NV34TCL_VTXBUF_ADDRESS(0), nv40->vtxelt->num_elements);
+	so_method(vtxbuf, eng3d, NV34TCL_VTXBUF_ADDRESS(0), nv40->vtxelt->num_elements);
 	vtxfmt = so_new(1, 16, 0);
-	so_method(vtxfmt, curie, NV34TCL_VTXFMT(0), nv40->vtxelt->num_elements);
+	so_method(vtxfmt, eng3d, NV34TCL_VTXFMT(0), nv40->vtxelt->num_elements);
 
 	for (hw = 0; hw < nv40->vtxelt->num_elements; hw++) {
 		struct pipe_vertex_element *ve;
@@ -534,13 +534,13 @@ nv40_vbo_validate(struct nv40_context *nv40)
 	if (ib) {
 		struct nouveau_bo *bo = nouveau_bo(ib);
 
-		so_method(vtxbuf, curie, NV34TCL_IDXBUF_ADDRESS, 2);
+		so_method(vtxbuf, eng3d, NV34TCL_IDXBUF_ADDRESS, 2);
 		so_reloc (vtxbuf, bo, 0, vb_flags | NOUVEAU_BO_LOW, 0, 0);
 		so_reloc (vtxbuf, bo, ib_format, vb_flags | NOUVEAU_BO_OR,
 			  0, NV34TCL_IDXBUF_FORMAT_DMA1);
 	}
 
-	so_method(vtxbuf, curie, 0x1710, 1);
+	so_method(vtxbuf, eng3d, 0x1710, 1);
 	so_data  (vtxbuf, 0);
 
 	so_ref(vtxbuf, &nv40->state.hw[NV40_STATE_VTXBUF]);
diff --git a/src/gallium/drivers/nv40/nv40_vertprog.c b/src/gallium/drivers/nv40/nv40_vertprog.c
index 2abda14f31..96f2743429 100644
--- a/src/gallium/drivers/nv40/nv40_vertprog.c
+++ b/src/gallium/drivers/nv40/nv40_vertprog.c
@@ -836,7 +836,7 @@ nv40_vertprog_validate(struct nv40_context *nv40)
 	struct pipe_screen *pscreen = nv40->pipe.screen;
 	struct nv40_screen *screen = nv40->screen;
 	struct nouveau_channel *chan = screen->base.channel;
-	struct nouveau_grobj *curie = screen->curie;
+	struct nouveau_grobj *eng3d = screen->eng3d;
 	struct nv40_vertex_program *vp;
 	struct pipe_buffer *constbuf;
 	boolean upload_code = FALSE, upload_data = FALSE;
@@ -887,12 +887,12 @@ check_gpu_resources:
 		}
 
 		so = so_new(3, 4, 0);
-		so_method(so, curie, NV34TCL_VP_START_FROM_ID, 1);
+		so_method(so, eng3d, NV34TCL_VP_START_FROM_ID, 1);
 		so_data  (so, vp->exec->start);
-		so_method(so, curie, NV40TCL_VP_ATTRIB_EN, 2);
+		so_method(so, eng3d, NV40TCL_VP_ATTRIB_EN, 2);
 		so_data  (so, vp->ir);
 		so_data  (so, vp->or);
-		so_method(so, curie,  NV34TCL_VP_CLIP_PLANES_ENABLE, 1);
+		so_method(so, eng3d,  NV34TCL_VP_CLIP_PLANES_ENABLE, 1);
 		so_data  (so, vp->clip_ctrl);
 		so_ref(so, &vp->so);
 		so_ref(NULL, &so);
@@ -976,7 +976,7 @@ check_gpu_resources:
 				       4 * sizeof(float));
 			}
 
-			BEGIN_RING(chan, curie, NV34TCL_VP_UPLOAD_CONST_ID, 5);
+			BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_CONST_ID, 5);
 			OUT_RING  (chan, i + vp->data->start);
 			OUT_RINGp (chan, (uint32_t *)vpd->value, 4);
 		}
@@ -995,10 +995,10 @@ check_gpu_resources:
 			NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[3]);
 		}
 #endif
-		BEGIN_RING(chan, curie, NV34TCL_VP_UPLOAD_FROM_ID, 1);
+		BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_FROM_ID, 1);
 		OUT_RING  (chan, vp->exec->start);
 		for (i = 0; i < vp->nr_insns; i++) {
-			BEGIN_RING(chan, curie, NV34TCL_VP_UPLOAD_INST(0), 4);
+			BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_INST(0), 4);
 			OUT_RINGp (chan, vp->insns[i].data, 4);
 		}
 	}