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authorMichal Krol <michal@vmware.com>2010-11-04 11:51:10 +0100
committerMichal Krol <michal@vmware.com>2010-11-04 11:51:10 +0100
commitf93d6f929f2439f87950df2c30c6c48b6dcac395 (patch)
treea80471ffbd1c50e75b29acf2c1851884afc137e8
parentee9366ab363a71407e4806ce079f98fc064d8734 (diff)
tgsi/exec: Get rid of obsolete condition codes.
-rw-r--r--src/gallium/auxiliary/tgsi/tgsi_exec.c10
-rw-r--r--src/gallium/auxiliary/tgsi/tgsi_exec.h27
2 files changed, 4 insertions, 33 deletions
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index 57ae56e96f..7892a67f04 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -477,8 +477,6 @@ enum tgsi_exec_datatype {
#define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
#define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
#define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
-#define TEMP_CC_I TGSI_EXEC_TEMP_CC_I
-#define TEMP_CC_C TGSI_EXEC_TEMP_CC_C
/** The execution mask depends on the conditional mask and the loop mask */
@@ -3719,14 +3717,6 @@ tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
mach->Primitives[0] = 0;
}
- for (i = 0; i < QUAD_SIZE; i++) {
- mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C].u[i] =
- (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_X_SHIFT) |
- (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Y_SHIFT) |
- (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_Z_SHIFT) |
- (TGSI_EXEC_CC_EQ << TGSI_EXEC_CC_W_SHIFT);
- }
-
/* execute declarations (interpolants) */
for (i = 0; i < mach->NumDeclarations; i++) {
exec_declaration( mach, mach->Declarations+i );
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index 9d62c1d7e7..bd5492e949 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
@@ -131,34 +131,15 @@ struct tgsi_sampler
#define TGSI_EXEC_TEMP_PRIMITIVE_I (TGSI_EXEC_NUM_TEMPS + 2)
#define TGSI_EXEC_TEMP_PRIMITIVE_C 2
-/* NVIDIA condition code (CC) vector
- */
-#define TGSI_EXEC_CC_GT 0x01
-#define TGSI_EXEC_CC_EQ 0x02
-#define TGSI_EXEC_CC_LT 0x04
-#define TGSI_EXEC_CC_UN 0x08
-
-#define TGSI_EXEC_CC_X_MASK 0x000000ff
-#define TGSI_EXEC_CC_X_SHIFT 0
-#define TGSI_EXEC_CC_Y_MASK 0x0000ff00
-#define TGSI_EXEC_CC_Y_SHIFT 8
-#define TGSI_EXEC_CC_Z_MASK 0x00ff0000
-#define TGSI_EXEC_CC_Z_SHIFT 16
-#define TGSI_EXEC_CC_W_MASK 0xff000000
-#define TGSI_EXEC_CC_W_SHIFT 24
-
-#define TGSI_EXEC_TEMP_CC_I (TGSI_EXEC_NUM_TEMPS + 2)
-#define TGSI_EXEC_TEMP_CC_C 3
-
-#define TGSI_EXEC_TEMP_THREE_I (TGSI_EXEC_NUM_TEMPS + 3)
-#define TGSI_EXEC_TEMP_THREE_C 0
+#define TGSI_EXEC_TEMP_THREE_I (TGSI_EXEC_NUM_TEMPS + 2)
+#define TGSI_EXEC_TEMP_THREE_C 3
#define TGSI_EXEC_TEMP_HALF_I (TGSI_EXEC_NUM_TEMPS + 3)
-#define TGSI_EXEC_TEMP_HALF_C 1
+#define TGSI_EXEC_TEMP_HALF_C 0
/* execution mask, each value is either 0 or ~0 */
#define TGSI_EXEC_MASK_I (TGSI_EXEC_NUM_TEMPS + 3)
-#define TGSI_EXEC_MASK_C 2
+#define TGSI_EXEC_MASK_C 1
/* 4 register buffer for various purposes */
#define TGSI_EXEC_TEMP_R0 (TGSI_EXEC_NUM_TEMPS + 4)