Merge branch 'gallium-0.1' into gallium-0.2

A first attempt at moving gallium onto a branch directly off master...

It will be interesting to see how much work this takes to get running.

Have resolved the conflicts semi-arbitarily, not compiled or tested.

Conflicts:

	.gitignore
	Makefile
	configs/config.mgw
	configs/darwin
	configs/darwin-x86ppc
	configs/default
	configs/freebsd-dri
	configs/linux-dri
	configs/linux-dri-xcb
	configs/linux-fbdev
	configs/linux-static
	configs/linux-x86-64-static
	configs/linux-x86-static
	doxygen/Makefile
	include/GL/gl.h
	progs/demos/Makefile
	progs/demos/descrip.mms
	progs/demos/texenv.c
	progs/egl/.gitignore
	progs/egl/Makefile
	progs/glsl/.gitignore
	progs/glsl/Makefile
	progs/glsl/convolutions.c
	progs/samples/Makefile.mgw
	progs/tests/.gitignore
	progs/trivial/.gitignore
	progs/trivial/point-param.c
	progs/trivial/tri.c
	progs/xdemos/.gitignore
	progs/xdemos/glthreads.c
	src/egl/drivers/demo/Makefile
	src/egl/drivers/dri/Makefile
	src/egl/main/Makefile
	src/glu/Makefile
	src/glu/sgi/Makefile
	src/glu/sgi/Makefile.mgw
	src/glut/glx/Makefile.mgw
	src/glut/os2/WarpWin.cpp
	src/glut/os2/glut_cindex.cpp
	src/glut/os2/glut_gamemode.cpp
	src/glut/os2/glut_win.cpp
	src/glut/os2/glut_winmisc.cpp
	src/glut/os2/os2_glx.cpp
	src/glut/os2/os2_menu.cpp
	src/glut/os2/os2_winproc.cpp
	src/glw/Makefile
	src/glx/x11/dri_glx.c
	src/glx/x11/glxext.c
	src/mesa/Makefile
	src/mesa/Makefile.mgw
	src/mesa/descrip.mms
	src/mesa/drivers/beos/Makefile
	src/mesa/drivers/common/descrip.mms
	src/mesa/drivers/common/driverfuncs.c
	src/mesa/drivers/directfb/Makefile
	src/mesa/drivers/dri/Makefile.template
	src/mesa/drivers/dri/common/dri_bufmgr.c
	src/mesa/drivers/dri/common/dri_bufmgr.h
	src/mesa/drivers/dri/common/dri_util.c
	src/mesa/drivers/dri/common/extension_helper.h
	src/mesa/drivers/dri/common/mmio.h
	src/mesa/drivers/dri/common/utils.c
	src/mesa/drivers/dri/common/utils.h
	src/mesa/drivers/dri/glcore/Makefile
	src/mesa/drivers/dri/i810/i810screen.c
	src/mesa/drivers/dri/i915/intel_ioctl.c
	src/mesa/drivers/dri/i915/intel_ioctl.h
	src/mesa/drivers/dri/i915/intel_screen.c
	src/mesa/drivers/dri/i915/server/i830_common.h
	src/mesa/drivers/dri/i915/server/i830_dri.h
	src/mesa/drivers/dri/i965/intel_screen.c
	src/mesa/drivers/dri/i965/server/i830_common.h
	src/mesa/drivers/dri/i965/server/i830_dri.h
	src/mesa/drivers/dri/mach64/mach64_screen.c
	src/mesa/drivers/dri/nouveau/nouveau_context.h
	src/mesa/drivers/dri/nouveau/nouveau_fifo.c
	src/mesa/drivers/dri/nouveau/nouveau_fifo.h
	src/mesa/drivers/dri/nouveau/nouveau_screen.c
	src/mesa/drivers/dri/nouveau/nouveau_screen.h
	src/mesa/drivers/dri/r128/r128_tex.h
	src/mesa/drivers/dri/savage/savageioctl.h
	src/mesa/drivers/fbdev/Makefile
	src/mesa/drivers/osmesa/Makefile
	src/mesa/drivers/osmesa/descrip.mms
	src/mesa/drivers/x11/Makefile
	src/mesa/drivers/x11/descrip.mms
	src/mesa/drivers/x11/xm_dd.c
	src/mesa/glapi/glapi.c
	src/mesa/glapi/glthread.c
	src/mesa/main/api_validate.c
	src/mesa/main/attrib.c
	src/mesa/main/bufferobj.c
	src/mesa/main/bufferobj.h
	src/mesa/main/buffers.c
	src/mesa/main/config.h
	src/mesa/main/context.c
	src/mesa/main/descrip.mms
	src/mesa/main/drawpix.c
	src/mesa/main/enums.c
	src/mesa/main/fbobject.c
	src/mesa/main/glheader.h
	src/mesa/main/imports.c
	src/mesa/main/mipmap.c
	src/mesa/main/mm.c
	src/mesa/main/mm.h
	src/mesa/main/mtypes.h
	src/mesa/main/points.c
	src/mesa/main/sources
	src/mesa/main/state.c
	src/mesa/main/texcompress_fxt1.c
	src/mesa/main/texenvprogram.c
	src/mesa/main/texobj.c
	src/mesa/main/texstate.c
	src/mesa/main/texstore.c
	src/mesa/math/descrip.mms
	src/mesa/shader/arbprogram.c
	src/mesa/shader/descrip.mms
	src/mesa/shader/prog_execute.c
	src/mesa/shader/prog_statevars.c
	src/mesa/shader/prog_statevars.h
	src/mesa/shader/prog_uniform.c
	src/mesa/shader/program.c
	src/mesa/shader/program.h
	src/mesa/shader/shader_api.c
	src/mesa/shader/slang/descrip.mms
	src/mesa/shader/slang/library/slang_vertex_builtin_gc.h
	src/mesa/sources
	src/mesa/swrast/descrip.mms
	src/mesa/swrast/s_drawpix.c
	src/mesa/swrast/s_fragprog.c
	src/mesa/swrast/s_readpix.c
	src/mesa/swrast/s_span.c
	src/mesa/swrast_setup/descrip.mms
	src/mesa/tnl/descrip.mms
	src/mesa/tnl/t_context.h
	src/mesa/tnl/t_vp_build.c
	src/mesa/tnl/tnl.h
	src/mesa/vbo/descrip.mms
	src/mesa/vbo/vbo_context.c
	src/mesa/vbo/vbo_exec_array.c
	src/mesa/x86-64/xform4.S
	src/mesa/x86/rtasm/x86sse.c
	src/mesa/x86/rtasm/x86sse.h
	windows/VC6/progs/glut/glut.dsp
	windows/VC7/mesa/gdi/gdi.vcproj
	windows/VC7/mesa/glu/glu.vcproj
	windows/VC7/mesa/mesa.sln
	windows/VC7/mesa/mesa/mesa.vcproj
	windows/VC7/mesa/osmesa/osmesa.vcproj
	windows/VC7/progs/glut/glut.vcproj
	windows/VC8/mesa/gdi/gdi.vcproj
	windows/VC8/mesa/glu/glu.vcproj
	windows/VC8/mesa/mesa.sln
	windows/VC8/mesa/mesa/mesa.vcproj
	windows/VC8/progs/glut/glut.vcproj

1 files changed, 211 insertions, 0 deletions

diff --git a/src/gallium/drivers/cell/spu/spu_per_fragment_op.c b/src/gallium/drivers/cell/spu/spu_per_fragment_op.c
new file mode 100644
index 0000000000..b4cffeeb32
--- /dev/null
+++ b/src/gallium/drivers/cell/spu/spu_per_fragment_op.c
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright IBM Corporation 2008
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
+ * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * \file spu_per_fragment_op.c
+ * SPU implementation various per-fragment operations.
+ *
+ * \author Ian Romanick <idr@us.ibm.com>
+ */
+
+#include "pipe/p_format.h"
+#include "spu_main.h"
+#include "spu_per_fragment_op.h"
+
+#define ZERO 0x80
+
+static void
+read_ds_quad(tile_t *buffer, unsigned x, unsigned y,
+             enum pipe_format depth_format, qword *depth,
+             qword *stencil)
+{
+   const int ix = x / 2;
+   const int iy = y / 2;
+
+   switch (depth_format) {
+   case PIPE_FORMAT_Z16_UNORM: {
+      qword *ptr = (qword *) &buffer->us8[iy][ix / 2];
+
+      const qword shuf_vec = (qword) {
+         ZERO, ZERO, 0, 1, ZERO, ZERO, 2, 3,
+         ZERO, ZERO, 4, 5, ZERO, ZERO, 6, 7
+      };
+
+
+      /* At even X values we want the first 4 shorts, and at odd X values we
+       * want the second 4 shorts.
+       */
+      qword bias = (qword) spu_splats((unsigned char) ((ix & 0x01) << 3));
+      qword bias_mask = si_fsmbi(0x3333);
+      qword sv = si_a(shuf_vec, si_and(bias_mask, bias));
+
+      *depth = si_shufb(*ptr, *ptr, sv);
+      *stencil = si_il(0);
+      break;
+   }
+
+
+   case PIPE_FORMAT_Z32_UNORM: {
+      qword *ptr = (qword *) &buffer->ui4[iy][ix];
+
+      *depth = *ptr;
+      *stencil = si_il(0);
+      break;
+   }
+      
+
+   case PIPE_FORMAT_Z24S8_UNORM: {
+      qword *ptr = (qword *) &buffer->ui4[iy][ix];
+      qword mask = si_fsmbi(0xEEEE);
+
+      *depth = si_rotmai(si_and(*ptr, mask), -8);
+      *stencil = si_andc(*ptr, mask);
+      break;
+   }
+
+
+   case PIPE_FORMAT_S8Z24_UNORM: {
+      qword *ptr = (qword *) &buffer->ui4[iy][ix];
+
+      *depth = si_and(*ptr, si_fsmbi(0x7777));
+      *stencil = si_andi(si_roti(*ptr, 8), 0x0ff);
+      break;
+   }
+
+
+   default:
+      assert(0);
+      break;
+   }
+}
+
+
+static void
+write_ds_quad(tile_t *buffer, unsigned x, unsigned y,
+              enum pipe_format depth_format,
+              qword depth, qword stencil)
+{
+   const int ix = x / 2;
+   const int iy = y / 2;
+
+   (void) stencil;
+
+   switch (depth_format) {
+   case PIPE_FORMAT_Z16_UNORM: {
+      qword *ptr = (qword *) &buffer->us8[iy][ix / 2];
+
+      qword sv = ((ix & 0x01) == 0) 
+          ? (qword) { 2, 3, 6, 7, 10, 11, 14, 15,
+                      24, 25, 26, 27, 28, 29, 30, 31 }
+          : (qword) { 16, 17, 18, 19, 20 , 21, 22, 23,
+                      2, 3, 6, 7, 10, 11, 14, 15 };
+      *ptr = si_shufb(depth, *ptr, sv);
+      break;
+   }
+
+
+   case PIPE_FORMAT_Z32_UNORM: {
+      qword *ptr = (qword *) &buffer->ui4[iy][ix];
+      *ptr = depth;
+      break;
+   }
+
+
+   case PIPE_FORMAT_Z24S8_UNORM: {
+      qword *ptr = (qword *) &buffer->ui4[iy][ix];
+      qword mask = si_fsmbi(0xEEEE);
+
+      depth = si_shli(depth, 8);
+      *ptr = si_selb(stencil, depth, mask);
+      break;
+   }
+
+
+   case PIPE_FORMAT_S8Z24_UNORM: {
+      qword *ptr = (qword *) &buffer->ui4[iy][ix];
+      qword mask = si_fsmbi(0x7777);
+
+      stencil = si_shli(stencil, 24);
+      *ptr = si_selb(stencil, depth, mask);
+      break;
+   }
+
+
+   default:
+      assert(0);
+      break;
+   }
+}
+
+
+qword
+spu_do_depth_stencil(int x, int y,
+                     qword frag_mask, qword frag_depth, qword frag_alpha,
+                     qword facing)
+{
+   struct spu_frag_test_results  result;
+   qword pixel_depth;
+   qword pixel_stencil;
+
+   /* All of this preable code (everthing before the call to frag_test) should
+    * be generated on the PPU and upload to the SPU.
+    */
+   if (spu.read_depth || spu.read_stencil) {
+      read_ds_quad(&spu.ztile, x, y, spu.fb.depth_format,
+                   &pixel_depth, &pixel_stencil);
+   }
+   
+   switch (spu.fb.depth_format) {
+   case PIPE_FORMAT_Z16_UNORM:
+      frag_depth = si_fm(frag_depth, (qword)spu_splats((float)(0x0000ffffu)));
+      frag_depth = si_cfltu(frag_depth, 0);
+      break;
+   case PIPE_FORMAT_Z32_UNORM:
+      frag_depth = si_fm(frag_depth, (qword)spu_splats((float)(0xffffffffu)));
+      frag_depth = si_cfltu(frag_depth, 0);
+      break;
+   case PIPE_FORMAT_Z24S8_UNORM:
+   case PIPE_FORMAT_S8Z24_UNORM:
+      frag_depth = si_fm(frag_depth, (qword)spu_splats((float)(0x00ffffffu)));
+      frag_depth = si_cfltu(frag_depth, 0);
+      break;
+   default:
+      ASSERT(0);
+      break;
+   }
+
+   result = (*spu.frag_test)(frag_mask, pixel_depth, pixel_stencil,
+                             frag_depth, frag_alpha, facing);
+
+
+   /* This code (everthing after the call to frag_test) should
+    * be generated on the PPU and upload to the SPU.
+    */
+   if (spu.read_depth || spu.read_stencil) {
+      write_ds_quad(&spu.ztile, x, y, spu.fb.depth_format,
+                    result.depth, result.stencil);
+   }
+
+   return result.mask;
+}