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authorRoland Scheidegger <sroland@vmware.com>2010-06-05 16:49:51 +0200
committerRoland Scheidegger <sroland@vmware.com>2010-06-05 16:54:36 +0200
commitb6cd0712e9961c5cfbc94b5e59467ed90aeb3a2f (patch)
tree542f1453667c046add75da4c82c55923fd2ac7c4 /src/gallium/drivers/i915
parentc00065e5c2ba8a1bcaa543b079abc883af0844f3 (diff)
i915g: fix bug in ds clear logic (still disabled)
Diffstat (limited to 'src/gallium/drivers/i915')
-rw-r--r--src/gallium/drivers/i915/i915_surface.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/i915/i915_surface.c b/src/gallium/drivers/i915/i915_surface.c
index 7869be8f68..f40876e708 100644
--- a/src/gallium/drivers/i915/i915_surface.c
+++ b/src/gallium/drivers/i915/i915_surface.c
@@ -143,8 +143,8 @@ i915_clear_depth_stencil(struct pipe_context *pipe,
/* XXX presumably this does read-modify-write
(otherwise this won't work anyway). Hence will only want to
do it if really have stencil and it isn't cleared */
- if (!((clear_flags & PIPE_CLEAR_STENCIL) ||
- (dst->format != PIPE_FORMAT_Z24_UNORM_S8_USCALED)))
+ if ((clear_flags & PIPE_CLEAR_STENCIL) ||
+ (dst->format != PIPE_FORMAT_Z24_UNORM_S8_USCALED))
mask |= XY_COLOR_BLT_WRITE_ALPHA;
i915_fill_blit( i915_context(pipe),