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authorDave Airlie <airlied@gmail.com>2010-12-30 19:16:16 +1000
committerDave Airlie <airlied@gmail.com>2011-01-09 17:21:10 +1000
commit5826967d2e6131714081287be5425b68702f1ca5 (patch)
treecd41c7fac8805d77263dad31c1d3f12aa9e059b2 /src/gallium/drivers/i965/brw_clip.c
parent3332229b3ba7a183a9f120ae4bbf9865e96df110 (diff)
i965g: update to similiar gen stuff as i965
Diffstat (limited to 'src/gallium/drivers/i965/brw_clip.c')
-rw-r--r--src/gallium/drivers/i965/brw_clip.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/gallium/drivers/i965/brw_clip.c b/src/gallium/drivers/i965/brw_clip.c
index ccba205e8c..66b13ea58e 100644
--- a/src/gallium/drivers/i965/brw_clip.c
+++ b/src/gallium/drivers/i965/brw_clip.c
@@ -66,16 +66,14 @@ compile_clip_prog( struct brw_context *brw,
c.func.single_program_flow = 1;
- c.chipset = brw->chipset;
c.key = *key;
- c.need_ff_sync = c.chipset.is_igdng;
/* Need to locate the two positions present in vertex + header.
* These are currently hardcoded:
*/
c.header_position_offset = ATTR_SIZE;
- if (c.chipset.is_igdng)
+ if (brw->gen == 5)
delta = 3 * REG_SIZE;
else
delta = REG_SIZE;
@@ -97,7 +95,7 @@ compile_clip_prog( struct brw_context *brw,
if (c.key.output_edgeflag != BRW_OUTPUT_NOT_PRESENT)
c.offset_edgeflag = delta + c.key.output_edgeflag * ATTR_SIZE;
- if (BRW_IS_IGDNG(brw))
+ if (brw->gen == 5)
c.nr_regs = (c.key.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */
else
c.nr_regs = (c.key.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */