i965g: pass backbuffer tiling information to driver

The gem winsys gets this information, needs to pass it on.

1 files changed, 3 insertions, 9 deletions

diff --git a/src/gallium/drivers/i965/brw_screen_texture.c b/src/gallium/drivers/i965/brw_screen_texture.c
index 666ec70d42..650cac240b 100644
--- a/src/gallium/drivers/i965/brw_screen_texture.c
+++ b/src/gallium/drivers/i965/brw_screen_texture.c
@@ -472,7 +472,8 @@ boolean brw_texture_get_winsys_buffer(struct pipe_texture *texture,
 struct pipe_texture * 
 brw_texture_blanket_winsys_buffer(struct pipe_screen *screen,
                                   const struct pipe_texture *templ,
-                                  const unsigned pitch,
+                                  unsigned pitch,
+				  unsigned tiling,
                                   struct brw_winsys_buffer *buffer)
 {
    struct brw_screen *bscreen = brw_screen(screen);
@@ -495,18 +496,11 @@ brw_texture_blanket_winsys_buffer(struct pipe_screen *screen,
    tex->base.screen = screen;
 
    tex->cpp = pf_get_size(tex->base.format);
+   tex->tiling = tiling;
 
    make_empty_list(&tex->views[0]);
    make_empty_list(&tex->views[1]);
 
-   if (1)
-      tex->tiling = BRW_TILING_NONE;
-   else if (bscreen->chipset.is_965 &&
-            pf_is_depth_or_stencil(templ->format))
-      tex->tiling = BRW_TILING_Y;
-   else
-      tex->tiling = BRW_TILING_X;
-
    if (!brw_texture_layout(bscreen, tex))
       goto fail;