r600g: add script to generate header file with offsets into state objects.

This was inherently fragile as any changes to r600_states.h would also
need manual updating of all of the bits in radeon.h. Just add a simple
python script to do the conversion, its not hooked up to make at all.

This also will make adding evergreen a bit easier.

1 files changed, 523 insertions, 0 deletions

diff --git a/src/gallium/drivers/r600/r600_states_inc.h b/src/gallium/drivers/r600/r600_states_inc.h
new file mode 100644
index 0000000000..5367af5850
--- /dev/null
+++ b/src/gallium/drivers/r600/r600_states_inc.h
@@ -0,0 +1,523 @@
+/* This file is autogenerated from r600_states.h - do not edit directly */
+/* autogenerating script is gen_r600_states.py */
+
+/* R600_CONFIG */
+#define R600_CONFIG__SQ_CONFIG		0
+#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1		1
+#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2		2
+#define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT		3
+#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1		4
+#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2		5
+#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ		6
+#define R600_CONFIG__TA_CNTL_AUX		7
+#define R600_CONFIG__VC_ENHANCE		8
+#define R600_CONFIG__DB_DEBUG		9
+#define R600_CONFIG__DB_WATERMARKS		10
+#define R600_CONFIG__SX_MISC		11
+#define R600_CONFIG__SPI_THREAD_GROUPING		12
+#define R600_CONFIG__CB_SHADER_CONTROL		13
+#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE		14
+#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE		15
+#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE		16
+#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE		17
+#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE		18
+#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE		19
+#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE		20
+#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE		21
+#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE		22
+#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL		23
+#define R600_CONFIG__VGT_HOS_CNTL		24
+#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL		25
+#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL		26
+#define R600_CONFIG__VGT_HOS_REUSE_DEPTH		27
+#define R600_CONFIG__VGT_GROUP_PRIM_TYPE		28
+#define R600_CONFIG__VGT_GROUP_FIRST_DECR		29
+#define R600_CONFIG__VGT_GROUP_DECR		30
+#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL		31
+#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL		32
+#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL		33
+#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL		34
+#define R600_CONFIG__VGT_GS_MODE		35
+#define R600_CONFIG__PA_SC_MODE_CNTL		36
+#define R600_CONFIG__VGT_STRMOUT_EN		37
+#define R600_CONFIG__VGT_REUSE_OFF		38
+#define R600_CONFIG__VGT_VTX_CNT_EN		39
+#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN		40
+#define R600_CONFIG_SIZE		41
+#define R600_CONFIG_PM4 128		
+
+/* R600_CB_CNTL */
+#define R600_CB_CNTL__CB_CLEAR_RED		0
+#define R600_CB_CNTL__CB_CLEAR_GREEN		1
+#define R600_CB_CNTL__CB_CLEAR_BLUE		2
+#define R600_CB_CNTL__CB_CLEAR_ALPHA		3
+#define R600_CB_CNTL__CB_SHADER_MASK		4
+#define R600_CB_CNTL__CB_TARGET_MASK		5
+#define R600_CB_CNTL__CB_FOG_RED		6
+#define R600_CB_CNTL__CB_FOG_GREEN		7
+#define R600_CB_CNTL__CB_FOG_BLUE		8
+#define R600_CB_CNTL__CB_COLOR_CONTROL		9
+#define R600_CB_CNTL__PA_SC_AA_CONFIG		10
+#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX		11
+#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX		12
+#define R600_CB_CNTL__CB_CLRCMP_CONTROL		13
+#define R600_CB_CNTL__CB_CLRCMP_SRC		14
+#define R600_CB_CNTL__CB_CLRCMP_DST		15
+#define R600_CB_CNTL__CB_CLRCMP_MSK		16
+#define R600_CB_CNTL__PA_SC_AA_MASK		17
+#define R600_CB_CNTL_SIZE		18
+#define R600_CB_CNTL_PM4 128		
+
+/* R600_RASTERIZER */
+#define R600_RASTERIZER__SPI_INTERP_CONTROL_0		0
+#define R600_RASTERIZER__PA_CL_CLIP_CNTL		1
+#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL		2
+#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL		3
+#define R600_RASTERIZER__PA_CL_NANINF_CNTL		4
+#define R600_RASTERIZER__PA_SU_POINT_SIZE		5
+#define R600_RASTERIZER__PA_SU_POINT_MINMAX		6
+#define R600_RASTERIZER__PA_SU_LINE_CNTL		7
+#define R600_RASTERIZER__PA_SC_LINE_STIPPLE		8
+#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL		9
+#define R600_RASTERIZER__PA_SC_LINE_CNTL		10
+#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ		11
+#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ		12
+#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ		13
+#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ		14
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL		15
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP		16
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE		17
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET		18
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE		19
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET		20
+#define R600_RASTERIZER_SIZE		21
+#define R600_RASTERIZER_PM4 128		
+
+/* R600_VIEWPORT */
+#define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0		0
+#define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0		1
+#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0		2
+#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0		3
+#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0		4
+#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0		5
+#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0		6
+#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0		7
+#define R600_VIEWPORT__PA_CL_VTE_CNTL		8
+#define R600_VIEWPORT_SIZE		9
+#define R600_VIEWPORT_PM4 128		
+
+/* R600_SCISSOR */
+#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL		0
+#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR		1
+#define R600_SCISSOR__PA_SC_WINDOW_OFFSET		2
+#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL		3
+#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR		4
+#define R600_SCISSOR__PA_SC_CLIPRECT_RULE		5
+#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL		6
+#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR		7
+#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL		8
+#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR		9
+#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL		10
+#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR		11
+#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL		12
+#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR		13
+#define R600_SCISSOR__PA_SC_EDGERULE		14
+#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL		15
+#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR		16
+#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL		17
+#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR		18
+#define R600_SCISSOR_SIZE		19
+#define R600_SCISSOR_PM4 128		
+
+/* R600_BLEND */
+#define R600_BLEND__CB_BLEND_RED		0
+#define R600_BLEND__CB_BLEND_GREEN		1
+#define R600_BLEND__CB_BLEND_BLUE		2
+#define R600_BLEND__CB_BLEND_ALPHA		3
+#define R600_BLEND__CB_BLEND0_CONTROL		4
+#define R600_BLEND__CB_BLEND1_CONTROL		5
+#define R600_BLEND__CB_BLEND2_CONTROL		6
+#define R600_BLEND__CB_BLEND3_CONTROL		7
+#define R600_BLEND__CB_BLEND4_CONTROL		8
+#define R600_BLEND__CB_BLEND5_CONTROL		9
+#define R600_BLEND__CB_BLEND6_CONTROL		10
+#define R600_BLEND__CB_BLEND7_CONTROL		11
+#define R600_BLEND__CB_BLEND_CONTROL		12
+#define R600_BLEND_SIZE		13
+#define R600_BLEND_PM4 128		
+
+/* R600_DSA */
+#define R600_DSA__DB_STENCIL_CLEAR		0
+#define R600_DSA__DB_DEPTH_CLEAR		1
+#define R600_DSA__SX_ALPHA_TEST_CONTROL		2
+#define R600_DSA__DB_STENCILREFMASK		3
+#define R600_DSA__DB_STENCILREFMASK_BF		4
+#define R600_DSA__SX_ALPHA_REF		5
+#define R600_DSA__SPI_FOG_FUNC_SCALE		6
+#define R600_DSA__SPI_FOG_FUNC_BIAS		7
+#define R600_DSA__SPI_FOG_CNTL		8
+#define R600_DSA__DB_DEPTH_CONTROL		9
+#define R600_DSA__DB_SHADER_CONTROL		10
+#define R600_DSA__DB_RENDER_CONTROL		11
+#define R600_DSA__DB_RENDER_OVERRIDE		12
+#define R600_DSA__DB_SRESULTS_COMPARE_STATE1		13
+#define R600_DSA__DB_PRELOAD_CONTROL		14
+#define R600_DSA__DB_ALPHA_TO_MASK		15
+#define R600_DSA_SIZE		16
+#define R600_DSA_PM4 128		
+
+/* R600_VS_SHADER */
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_0		0
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_1		1
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_2		2
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_3		3
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_4		4
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_5		5
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_6		6
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_7		7
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_8		8
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_9		9
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_10		10
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_11		11
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_12		12
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_13		13
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_14		14
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_15		15
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_16		16
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_17		17
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_18		18
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_19		19
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_20		20
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_21		21
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_22		22
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_23		23
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_24		24
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_25		25
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_26		26
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_27		27
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_28		28
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_29		29
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_30		30
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_31		31
+#define R600_VS_SHADER__SPI_VS_OUT_ID_0		32
+#define R600_VS_SHADER__SPI_VS_OUT_ID_1		33
+#define R600_VS_SHADER__SPI_VS_OUT_ID_2		34
+#define R600_VS_SHADER__SPI_VS_OUT_ID_3		35
+#define R600_VS_SHADER__SPI_VS_OUT_ID_4		36
+#define R600_VS_SHADER__SPI_VS_OUT_ID_5		37
+#define R600_VS_SHADER__SPI_VS_OUT_ID_6		38
+#define R600_VS_SHADER__SPI_VS_OUT_ID_7		39
+#define R600_VS_SHADER__SPI_VS_OUT_ID_8		40
+#define R600_VS_SHADER__SPI_VS_OUT_ID_9		41
+#define R600_VS_SHADER__SPI_VS_OUT_CONFIG		42
+#define R600_VS_SHADER__SQ_PGM_START_VS		43
+#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS		44
+#define R600_VS_SHADER__SQ_PGM_START_FS		45
+#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS		46
+#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS		47
+#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS		48
+#define R600_VS_SHADER_SIZE		49
+#define R600_VS_SHADER_PM4 128		
+
+/* R600_PS_SHADER */
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0		0
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1		1
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_2		2
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_3		3
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_4		4
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_5		5
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_6		6
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_7		7
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_8		8
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_9		9
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_10		10
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_11		11
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_12		12
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_13		13
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_14		14
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_15		15
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_16		16
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_17		17
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_18		18
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_19		19
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_20		20
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_21		21
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_22		22
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_23		23
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_24		24
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_25		25
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_26		26
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_27		27
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_28		28
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29		29
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30		30
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31		31
+#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0		32
+#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1		33
+#define R600_PS_SHADER__SPI_INPUT_Z		34
+#define R600_PS_SHADER__SQ_PGM_START_PS		35
+#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS		36
+#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS		37
+#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS		38
+#define R600_PS_SHADER_SIZE		39
+#define R600_PS_SHADER_PM4 128		
+
+/* R600_PS_CONSTANT */
+#define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0		0
+#define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0		1
+#define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0		2
+#define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0		3
+#define R600_PS_CONSTANT_SIZE		4
+#define R600_PS_CONSTANT_PM4 128		
+
+/* R600_VS_CONSTANT */
+#define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256		0
+#define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256		1
+#define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256		2
+#define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256		3
+#define R600_VS_CONSTANT_SIZE		4
+#define R600_VS_CONSTANT_PM4 128		
+
+/* R600_UCP */
+#define R600_UCP__PA_CL_UCP0_X		0
+#define R600_UCP__PA_CL_UCP0_Y		1
+#define R600_UCP__PA_CL_UCP0_Z		2
+#define R600_UCP__PA_CL_UCP0_W		3
+#define R600_UCP__PA_CL_UCP1_X		4
+#define R600_UCP__PA_CL_UCP1_Y		5
+#define R600_UCP__PA_CL_UCP1_Z		6
+#define R600_UCP__PA_CL_UCP1_W		7
+#define R600_UCP__PA_CL_UCP2_X		8
+#define R600_UCP__PA_CL_UCP2_Y		9
+#define R600_UCP__PA_CL_UCP2_Z		10
+#define R600_UCP__PA_CL_UCP2_W		11
+#define R600_UCP__PA_CL_UCP3_X		12
+#define R600_UCP__PA_CL_UCP3_Y		13
+#define R600_UCP__PA_CL_UCP3_Z		14
+#define R600_UCP__PA_CL_UCP3_W		15
+#define R600_UCP__PA_CL_UCP4_X		16
+#define R600_UCP__PA_CL_UCP4_Y		17
+#define R600_UCP__PA_CL_UCP4_Z		18
+#define R600_UCP__PA_CL_UCP4_W		19
+#define R600_UCP__PA_CL_UCP5_X		20
+#define R600_UCP__PA_CL_UCP5_Y		21
+#define R600_UCP__PA_CL_UCP5_Z		22
+#define R600_UCP__PA_CL_UCP5_W		23
+#define R600_UCP_SIZE		24
+#define R600_UCP_PM4 128		
+
+/* R600_PS_RESOURCE */
+#define R600_PS_RESOURCE__RESOURCE0_WORD0		0
+#define R600_PS_RESOURCE__RESOURCE0_WORD1		1
+#define R600_PS_RESOURCE__RESOURCE0_WORD2		2
+#define R600_PS_RESOURCE__RESOURCE0_WORD3		3
+#define R600_PS_RESOURCE__RESOURCE0_WORD4		4
+#define R600_PS_RESOURCE__RESOURCE0_WORD5		5
+#define R600_PS_RESOURCE__RESOURCE0_WORD6		6
+#define R600_PS_RESOURCE_SIZE		7
+#define R600_PS_RESOURCE_PM4 128		
+
+/* R600_VS_RESOURCE */
+#define R600_VS_RESOURCE__RESOURCE160_WORD0		0
+#define R600_VS_RESOURCE__RESOURCE160_WORD1		1
+#define R600_VS_RESOURCE__RESOURCE160_WORD2		2
+#define R600_VS_RESOURCE__RESOURCE160_WORD3		3
+#define R600_VS_RESOURCE__RESOURCE160_WORD4		4
+#define R600_VS_RESOURCE__RESOURCE160_WORD5		5
+#define R600_VS_RESOURCE__RESOURCE160_WORD6		6
+#define R600_VS_RESOURCE_SIZE		7
+#define R600_VS_RESOURCE_PM4 128		
+
+/* R600_FS_RESOURCE */
+#define R600_FS_RESOURCE__RESOURCE320_WORD0		0
+#define R600_FS_RESOURCE__RESOURCE320_WORD1		1
+#define R600_FS_RESOURCE__RESOURCE320_WORD2		2
+#define R600_FS_RESOURCE__RESOURCE320_WORD3		3
+#define R600_FS_RESOURCE__RESOURCE320_WORD4		4
+#define R600_FS_RESOURCE__RESOURCE320_WORD5		5
+#define R600_FS_RESOURCE__RESOURCE320_WORD6		6
+#define R600_FS_RESOURCE_SIZE		7
+#define R600_FS_RESOURCE_PM4 128		
+
+/* R600_GS_RESOURCE */
+#define R600_GS_RESOURCE__RESOURCE336_WORD0		0
+#define R600_GS_RESOURCE__RESOURCE336_WORD1		1
+#define R600_GS_RESOURCE__RESOURCE336_WORD2		2
+#define R600_GS_RESOURCE__RESOURCE336_WORD3		3
+#define R600_GS_RESOURCE__RESOURCE336_WORD4		4
+#define R600_GS_RESOURCE__RESOURCE336_WORD5		5
+#define R600_GS_RESOURCE__RESOURCE336_WORD6		6
+#define R600_GS_RESOURCE_SIZE		7
+#define R600_GS_RESOURCE_PM4 128		
+
+/* R600_PS_SAMPLER */
+#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0		0
+#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0		1
+#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0		2
+#define R600_PS_SAMPLER_SIZE		3
+#define R600_PS_SAMPLER_PM4 128		
+
+/* R600_VS_SAMPLER */
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18		0
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18		1
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18		2
+#define R600_VS_SAMPLER_SIZE		3
+#define R600_VS_SAMPLER_PM4 128		
+
+/* R600_GS_SAMPLER */
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36		0
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36		1
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36		2
+#define R600_GS_SAMPLER_SIZE		3
+#define R600_GS_SAMPLER_PM4 128		
+
+/* R600_PS_SAMPLER_BORDER */
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED		0
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN		1
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE		2
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA		3
+#define R600_PS_SAMPLER_BORDER_SIZE		4
+#define R600_PS_SAMPLER_BORDER_PM4 128		
+
+/* R600_VS_SAMPLER_BORDER */
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED		0
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN		1
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE		2
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA		3
+#define R600_VS_SAMPLER_BORDER_SIZE		4
+#define R600_VS_SAMPLER_BORDER_PM4 128		
+
+/* R600_GS_SAMPLER_BORDER */
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED		0
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN		1
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE		2
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA		3
+#define R600_GS_SAMPLER_BORDER_SIZE		4
+#define R600_GS_SAMPLER_BORDER_PM4 128		
+
+/* R600_CB0 */
+#define R600_CB0__CB_COLOR0_BASE		0
+#define R600_CB0__CB_COLOR0_INFO		1
+#define R600_CB0__CB_COLOR0_SIZE		2
+#define R600_CB0__CB_COLOR0_VIEW		3
+#define R600_CB0__CB_COLOR0_FRAG		4
+#define R600_CB0__CB_COLOR0_TILE		5
+#define R600_CB0__CB_COLOR0_MASK		6
+#define R600_CB0_SIZE		7
+#define R600_CB0_PM4 128		
+
+/* R600_CB1 */
+#define R600_CB1__CB_COLOR1_BASE		0
+#define R600_CB1__CB_COLOR1_INFO		1
+#define R600_CB1__CB_COLOR1_SIZE		2
+#define R600_CB1__CB_COLOR1_VIEW		3
+#define R600_CB1__CB_COLOR1_FRAG		4
+#define R600_CB1__CB_COLOR1_TILE		5
+#define R600_CB1__CB_COLOR1_MASK		6
+#define R600_CB1_SIZE		7
+#define R600_CB1_PM4 128		
+
+/* R600_CB2 */
+#define R600_CB2__CB_COLOR2_BASE		0
+#define R600_CB2__CB_COLOR2_INFO		1
+#define R600_CB2__CB_COLOR2_SIZE		2
+#define R600_CB2__CB_COLOR2_VIEW		3
+#define R600_CB2__CB_COLOR2_FRAG		4
+#define R600_CB2__CB_COLOR2_TILE		5
+#define R600_CB2__CB_COLOR2_MASK		6
+#define R600_CB2_SIZE		7
+#define R600_CB2_PM4 128		
+
+/* R600_CB3 */
+#define R600_CB3__CB_COLOR3_BASE		0
+#define R600_CB3__CB_COLOR3_INFO		1
+#define R600_CB3__CB_COLOR3_SIZE		2
+#define R600_CB3__CB_COLOR3_VIEW		3
+#define R600_CB3__CB_COLOR3_FRAG		4
+#define R600_CB3__CB_COLOR3_TILE		5
+#define R600_CB3__CB_COLOR3_MASK		6
+#define R600_CB3_SIZE		7
+#define R600_CB3_PM4 128		
+
+/* R600_CB4 */
+#define R600_CB4__CB_COLOR4_BASE		0
+#define R600_CB4__CB_COLOR4_INFO		1
+#define R600_CB4__CB_COLOR4_SIZE		2
+#define R600_CB4__CB_COLOR4_VIEW		3
+#define R600_CB4__CB_COLOR4_FRAG		4
+#define R600_CB4__CB_COLOR4_TILE		5
+#define R600_CB4__CB_COLOR4_MASK		6
+#define R600_CB4_SIZE		7
+#define R600_CB4_PM4 128		
+
+/* R600_CB5 */
+#define R600_CB5__CB_COLOR5_BASE		0
+#define R600_CB5__CB_COLOR5_INFO		1
+#define R600_CB5__CB_COLOR5_SIZE		2
+#define R600_CB5__CB_COLOR5_VIEW		3
+#define R600_CB5__CB_COLOR5_FRAG		4
+#define R600_CB5__CB_COLOR5_TILE		5
+#define R600_CB5__CB_COLOR5_MASK		6
+#define R600_CB5_SIZE		7
+#define R600_CB5_PM4 128		
+
+/* R600_CB6 */
+#define R600_CB6__CB_COLOR6_BASE		0
+#define R600_CB6__CB_COLOR6_INFO		1
+#define R600_CB6__CB_COLOR6_SIZE		2
+#define R600_CB6__CB_COLOR6_VIEW		3
+#define R600_CB6__CB_COLOR6_FRAG		4
+#define R600_CB6__CB_COLOR6_TILE		5
+#define R600_CB6__CB_COLOR6_MASK		6
+#define R600_CB6_SIZE		7
+#define R600_CB6_PM4 128		
+
+/* R600_CB7 */
+#define R600_CB7__CB_COLOR7_BASE		0
+#define R600_CB7__CB_COLOR7_INFO		1
+#define R600_CB7__CB_COLOR7_SIZE		2
+#define R600_CB7__CB_COLOR7_VIEW		3
+#define R600_CB7__CB_COLOR7_FRAG		4
+#define R600_CB7__CB_COLOR7_TILE		5
+#define R600_CB7__CB_COLOR7_MASK		6
+#define R600_CB7_SIZE		7
+#define R600_CB7_PM4 128		
+
+/* R600_DB */
+#define R600_DB__DB_DEPTH_BASE		0
+#define R600_DB__DB_DEPTH_SIZE		1
+#define R600_DB__DB_DEPTH_VIEW		2
+#define R600_DB__DB_DEPTH_INFO		3
+#define R600_DB__DB_HTILE_SURFACE		4
+#define R600_DB__DB_PREFETCH_LIMIT		5
+#define R600_DB_SIZE		6
+#define R600_DB_PM4 128		
+
+/* R600_VGT */
+#define R600_VGT__VGT_PRIMITIVE_TYPE		0
+#define R600_VGT__VGT_MAX_VTX_INDX		1
+#define R600_VGT__VGT_MIN_VTX_INDX		2
+#define R600_VGT__VGT_INDX_OFFSET		3
+#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX		4
+#define R600_VGT__VGT_DMA_INDEX_TYPE		5
+#define R600_VGT__VGT_PRIMITIVEID_EN		6
+#define R600_VGT__VGT_DMA_NUM_INSTANCES		7
+#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN		8
+#define R600_VGT__VGT_INSTANCE_STEP_RATE_0		9
+#define R600_VGT__VGT_INSTANCE_STEP_RATE_1		10
+#define R600_VGT_SIZE		11
+#define R600_VGT_PM4 128		
+
+/* R600_DRAW */
+#define R600_DRAW__VGT_NUM_INDICES		0
+#define R600_DRAW__VGT_DMA_BASE_HI		1
+#define R600_DRAW__VGT_DMA_BASE		2
+#define R600_DRAW__VGT_DRAW_INITIATOR		3
+#define R600_DRAW_SIZE		4
+#define R600_DRAW_PM4 128		
+
+/* R600_VGT_EVENT */
+#define R600_VGT_EVENT__VGT_EVENT_INITIATOR		0
+#define R600_VGT_EVENT_SIZE		1
+#define R600_VGT_EVENT_PM4 128		
+