glsl: Rework assignments with write_masks to have LHS chan count match RHS.

It turns out that most people new to this IR are surprised when an
assignment to (say) 3 components on the LHS takes 4 components on the
RHS.  It also makes for quite strange IR output:

(assign (constant bool (1)) (x) (var_ref color) (swiz x (var_ref v) ))
(assign (constant bool (1)) (y) (var_ref color) (swiz yy (var_ref v) ))
(assign (constant bool (1)) (z) (var_ref color) (swiz zzz (var_ref v) ))

But even worse, even we get it wrong, as shown by this line of our
current step(float, vec4):

(assign (constant bool (1)) (w)
	(var_ref t)
	(expression float b2f (expression bool >=
		    (swiz w (var_ref x))(var_ref edge))))

where we try to assign a float to the writemasked-out x channel and
don't supply anything for the actual w channel we're writing.  Drivers
right now just get lucky since ir_to_mesa spams the float value across
all the source channels of a vec4.

Instead, the RHS will now have a number of components equal to the
number of components actually being written.  Hopefully this confuses
everyone less, and it also makes codegen for a scalar target simpler.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 240e7cd49a..fa246b5e57 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -646,6 +646,14 @@ public:
     * For non-vector types in the LHS, this field will be zero.  For vector
     * types, a bit will be set for each component that is written.  Note that
     * for \c vec2 and \c vec3 types only the lower bits will ever be set.
+    *
+    * A partially-set write mask means that each enabled channel gets
+    * the value from a consecutive channel of the rhs.  For example,
+    * to write just .xyw of gl_FrontColor with color:
+    *
+    * (assign (constant bool (1)) (xyw)
+    *     (var_ref gl_FragColor)
+    *     (swiz xyw (var_ref color)))
     */
    unsigned write_mask:4;
 };