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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-29 15:18:37 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-29 15:18:37 +0800 |
| commit | d4da253b298677c63def5f2f774608d660be31a1 (patch) | |
| tree | 776816d78c567a2dbfaa56fc90872c092454bb5b /src/glx | |
| parent | b27a809266bd664cd101fcfdf20886cc2b7df787 (diff) | |
Revert "i965: Always set tiling for depth buffer on sandybridge"
This reverts commit 0a1910c26760762eb8d67f68dfd87494ab479e38.
oops, shouldn't apply tiling depth buffer for other chips as well.
Diffstat (limited to 'src/glx')
0 files changed, 0 insertions, 0 deletions