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author | Eric Anholt <eric@anholt.net> | 2009-11-03 17:18:36 -0800 |
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committer | Eric Anholt <eric@anholt.net> | 2009-11-06 11:37:31 -0800 |
commit | 8e0f40d28777f1ae599a95312788fe29a0515a0d (patch) | |
tree | 4d606e40469a51808ed9541c8a67327c7341855b /src/mesa/drivers/dri/i915/i915_program.h | |
parent | caf3038123d6d29afd7d1f0cd6db98a2282c3ca1 (diff) |
intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.
This should do all the things that MI_FLUSH did, but it can be pipelined
so that further rendering isn't blocked on the flush completion unless
necessary.
Diffstat (limited to 'src/mesa/drivers/dri/i915/i915_program.h')
0 files changed, 0 insertions, 0 deletions