diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2008-01-29 11:13:53 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2008-01-29 11:13:53 +0800 |
| commit | 8e444fb9e2685e3eac42beb848b08e91dc20c88a (patch) | |
| tree | 66b9374213269fdf45de01ec08caf131b5f27fb8 /src/mesa/drivers/dri/i965/brw_clip_line.c | |
| parent | f09b2382e9a2c8f4302e644ea8c9cb7c933457a1 (diff) | |
i965: new integrated graphics chipset support
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_clip_line.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_clip_line.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c index 9ad00676d4..7d51cddfc3 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_line.c +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c @@ -148,10 +148,13 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) brw_clip_init_clipmask(c); /* -ve rhw workaround */ - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); - brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), - brw_imm_ud(1<<20)); - brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f)); + if (!BRW_IS_IGD(p->brw)) { + brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); + brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), + brw_imm_ud(1<<20)); + brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f)); + } + brw_set_predicate_control(p, BRW_PREDICATE_NONE); plane_loop = brw_DO(p, BRW_EXECUTE_1); |