i965: Use SENDC on the first render target write on gen6.

This is apparently required, as the thread will be initiated while it
still has dependencies, and this is what waits for those to be
resolved before writing color.

1 files changed, 5 insertions, 1 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index d5f24c263f..3744e813bb 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1735,7 +1735,11 @@ void brw_fb_WRITE(struct brw_compile *p,
    GLuint msg_control, msg_type;
    GLboolean header_present = GL_TRUE;
 
-   insn = next_insn(p, BRW_OPCODE_SEND);
+   if (intel->gen >= 6 && binding_table_index == 0) {
+      insn = next_insn(p, BRW_OPCODE_SENDC);
+   } else {
+      insn = next_insn(p, BRW_OPCODE_SEND);
+   }
    /* The execution mask is ignored for render target writes. */
    insn->header.predicate_control = 0;
    insn->header.compression_control = BRW_COMPRESSION_NONE;