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author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-17 12:45:01 +0800 |
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committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-28 15:58:19 +0800 |
commit | 8c31a4c3cf6655fe4db6befb4a7b029ada62aaf6 (patch) | |
tree | 20be0a63523db22f80185462cafb9badc61b21b0 /src/mesa/drivers/dri/i965/brw_wm_glsl.c | |
parent | b016a78b983295c112421c01d378fbe2862412d4 (diff) |
i965: enable accumulator update in PS kernel too on sandybridge
Accumulator update flag must be set for implicit update on sandybridge.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_glsl.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_glsl.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index f60245377e..1cbd5d2b55 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -711,6 +711,9 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack)); + if (intel->gen >= 6) + brw_set_acc_write_control(p, 1); + for (i = 0; i < c->nr_fp_insns; i++) { const struct prog_instruction *inst = &c->prog_instructions[i]; int dst_flags; |