Revert "intel: Always allocate miptrees from level 0, not tObj->BaseLevel."

This reverts commit 7ce6517f3ac41bf770ab39aba4509d4f535ef663.
This reverts commit d60145d06d999c5c76000499e6fa9351e11d17fa.

I was wrong about which generations supported baselevel adjustment --
it's just gen4, nothing earlier.  This meant that i915 would have
never used the mag filter when baselevel != 0.  Not a severe bug, but
not an intentional regression.  I think we can fix the performance
issue another way.

1 files changed, 5 insertions, 5 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 4570af66cd..e921d8a9a1 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -196,15 +196,15 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
    surf.ss1.base_addr = intelObj->mt->region->buffer->offset; /* reloc */
 
-   /* mip_count is #levels - 1 */
    surf.ss2.mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
-   surf.ss2.width = intelObj->mt->width0 - 1;
-   surf.ss2.height = intelObj->mt->height0 - 1;
+   surf.ss2.width = firstImage->Width - 1;
+   surf.ss2.height = firstImage->Height - 1;
    brw_set_surface_tiling(&surf, intelObj->mt->region->tiling);
    surf.ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1;
-   surf.ss3.depth = intelObj->mt->depth0 - 1;
-   surf.ss4.min_lod = tObj->BaseLevel;
+   surf.ss3.depth = firstImage->Depth - 1;
 
+   surf.ss4.min_lod = 0;
+ 
    if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
       surf.ss0.cube_pos_x = 1;
       surf.ss0.cube_pos_y = 1;