diff options
| author | Eric Anholt <eric@anholt.net> | 2010-09-04 20:54:52 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-09-07 13:00:22 -0700 |
| commit | 32b84ef4ca50998914184fc4600d8e43674a9a22 (patch) | |
| tree | 81e1e2979b30d06a770d29a2c842b31c86203fae /src/mesa/drivers/dri/i965 | |
| parent | c47b289972a6c5ca0e30ff5618418e5ca91bd1ec (diff) | |
i965: Make pixel_xy results UW.
There is a restriction on the destination of an operation involving a
vector immediate being 128-bit aligned and the destination horizontal
stride being equivalent to 2 bytes. Fixes bad pixel_x results from
gl_FragCoord, where each pair had the same value.
Diffstat (limited to 'src/mesa/drivers/dri/i965')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 811d108228..25a20e7604 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1211,6 +1211,8 @@ fs_visitor::emit_interpolation() this->current_annotation = "compute pixel centers"; this->pixel_x = fs_reg(this, glsl_type::uint_type); this->pixel_y = fs_reg(this, glsl_type::uint_type); + this->pixel_x.type = BRW_REGISTER_TYPE_UW; + this->pixel_y.type = BRW_REGISTER_TYPE_UW; emit(fs_inst(BRW_OPCODE_ADD, this->pixel_x, fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), |