Merge branch 'master' into i915-unification

Conflicts:

	src/mesa/drivers/dri/common/dri_drmpool.c
	src/mesa/drivers/dri/i915tex/i915_vtbl.c
	src/mesa/drivers/dri/i915tex/intel_batchbuffer.c
	src/mesa/drivers/dri/i915tex/intel_context.c

32 files changed, 501 insertions, 91 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c
index 83182270ea..9ad00676d4 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_line.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_line.c
@@ -130,6 +130,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
    struct brw_instruction *plane_loop;
    struct brw_instruction *plane_active;
    struct brw_instruction *is_negative;
+   struct brw_instruction *is_neg2;
    struct brw_instruction *not_culled;
    struct brw_reg v1_null_ud = retype(vec1(brw_null_reg()), BRW_REGISTER_TYPE_UD);
 
@@ -146,6 +147,13 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
    brw_clip_init_planes(c);
    brw_clip_init_clipmask(c);
 
+   /* -ve rhw workaround */
+   brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
+   brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
+	   brw_imm_ud(1<<20));
+   brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f));
+   brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+
    plane_loop = brw_DO(p, BRW_EXECUTE_1);
    {
       /* if (planemask & 1)
@@ -183,13 +191,20 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
 	    /* Coming back in.  We know that both cannot be negative
 	     * because the line would have been culled in that case.
 	     */
-	    brw_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1));
-	    brw_math_invert(p, c->reg.t, c->reg.t);
-	    brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp0);
 
-	    brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t0 );
-	    brw_MOV(p, c->reg.t0, c->reg.t);
-	    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+	    /* If both are positive, do nothing */
+             brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0, brw_imm_f(0.0));
+             is_neg2 = brw_IF(p, BRW_EXECUTE_1);
+             {
+		brw_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1));
+		brw_math_invert(p, c->reg.t, c->reg.t);
+		brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp0);
+
+		brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t0 );
+		brw_MOV(p, c->reg.t0, c->reg.t);
+		brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+	     }
+	     brw_ENDIF(p, is_neg2);
 	 }
 	 brw_ENDIF(p, is_negative);	 
       }
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 1e6d6fa176..ae46d7a86e 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -55,7 +55,7 @@ static void upload_clip_unit( struct brw_context *brw )
    /* BRW_NEW_URB_FENCE */
    clip.thread4.nr_urb_entries = brw->urb.nr_clip_entries; 
    clip.thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
-   clip.thread4.max_threads = 0; /* Hmm, maybe the max is 1 or 2 threads */
+   clip.thread4.max_threads = 1; /* 2 threads */
 
    if (INTEL_DEBUG & DEBUG_STATS)
       clip.thread4.stats_enable = 1; 
diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c
index f62b02cedf..506ab3712d 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
@@ -42,6 +42,20 @@
 #include "brw_util.h"
 #include "brw_clip.h"
 
+static struct brw_reg get_tmp( struct brw_clip_compile *c )
+{
+   struct brw_reg tmp = brw_vec4_grf(c->last_tmp, 0);
+
+   if (++c->last_tmp > c->prog_data.total_grf)
+      c->prog_data.total_grf = c->last_tmp;
+
+   return tmp;
+}
+
+static void release_tmps( struct brw_clip_compile *c )
+{
+   c->last_tmp = c->first_tmp;
+}
 
 
 void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, 
@@ -435,15 +449,103 @@ static void maybe_do_clip_tri( struct brw_clip_compile *c )
    brw_ENDIF(p, do_clip);
 }
 
-
+static void brw_clip_test( struct brw_clip_compile *c )
+{
+    struct brw_reg t = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
+    struct brw_reg t1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
+    struct brw_reg t2 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
+    struct brw_reg t3 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
+
+    struct brw_reg v0 = get_tmp(c);
+    struct brw_reg v1 = get_tmp(c);
+    struct brw_reg v2 = get_tmp(c);
+
+    struct brw_indirect vt0 = brw_indirect(0, 0);
+    struct brw_indirect vt1 = brw_indirect(1, 0);
+    struct brw_indirect vt2 = brw_indirect(2, 0);
+
+    struct brw_compile *p = &c->func;
+
+    brw_MOV(p, get_addr_reg(vt0), brw_address(c->reg.vertex[0]));
+    brw_MOV(p, get_addr_reg(vt1), brw_address(c->reg.vertex[1]));
+    brw_MOV(p, get_addr_reg(vt2), brw_address(c->reg.vertex[2]));
+    brw_MOV(p, v0, deref_4f(vt0, c->offset[VERT_RESULT_HPOS]));
+    brw_MOV(p, v1, deref_4f(vt1, c->offset[VERT_RESULT_HPOS]));
+    brw_MOV(p, v2, deref_4f(vt2, c->offset[VERT_RESULT_HPOS]));
+    brw_AND(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(~0x3f));
+
+    /* test nearz, xmin, ymin plane */
+    brw_CMP(p, t1, BRW_CONDITIONAL_LE, negate(v0), get_element(v0, 3)); 
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, t2, BRW_CONDITIONAL_LE, negate(v1), get_element(v1, 3)); 
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, t3, BRW_CONDITIONAL_LE, negate(v2), get_element(v2, 3)); 
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_XOR(p, t, t1, t2);
+    brw_XOR(p, t1, t2, t3);
+    brw_OR(p, t, t, t1);
+
+    brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, 
+	    get_element(t, 0), brw_imm_ud(0));
+    brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<5)));
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, 
+	    get_element(t, 1), brw_imm_ud(0));
+    brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<3)));
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, 
+	    get_element(t, 2), brw_imm_ud(0));
+    brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<1)));
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+
+    /* test farz, xmax, ymax plane */
+    brw_CMP(p, t1, BRW_CONDITIONAL_L, v0, get_element(v0, 3)); 
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, t2, BRW_CONDITIONAL_L, v1, get_element(v1, 3)); 
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, t3, BRW_CONDITIONAL_L, v2, get_element(v2, 3)); 
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+
+    brw_XOR(p, t, t1, t2);
+    brw_XOR(p, t1, t2, t3);
+    brw_OR(p, t, t, t1);
+
+    brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, 
+	    get_element(t, 0), brw_imm_ud(0));
+    brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<4)));
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, 
+	    get_element(t, 1), brw_imm_ud(0));
+    brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<2)));
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, 
+	    get_element(t, 2), brw_imm_ud(0));
+    brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<0)));
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+
+    release_tmps(c);
+}
 
 
 void brw_emit_tri_clip( struct brw_clip_compile *c )
 {
+   struct brw_instruction *neg_rhw;
+   struct brw_compile *p = &c->func;
    brw_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6);
    brw_clip_tri_init_vertices(c);
    brw_clip_init_clipmask(c);
 
+   /* if -ve rhw workaround bit is set, 
+      do cliptest */
+   brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
+   brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), 
+	   brw_imm_ud(1<<20));
+   neg_rhw = brw_IF(p, BRW_EXECUTE_1); 
+   {
+       brw_clip_test(c);
+   }
+   brw_ENDIF(p, neg_rhw);
+
    /* Can't push into do_clip_tri because with polygon (or quad)
     * flatshading, need to apply the flatshade here because we don't
     * respect the PV when converting to trifan for emit:
@@ -462,6 +564,3 @@ void brw_emit_tri_clip( struct brw_clip_compile *c )
     */
    brw_clip_kill_thread(c);
 }
-
-
-
diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c
index 19bef19801..c37bfeb1ce 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
@@ -272,6 +272,7 @@ void brw_clip_kill_thread(struct brw_clip_compile *c)
 
 
 
+
 struct brw_reg brw_clip_plane0_address( struct brw_clip_compile *c )
 {
    return brw_address(c->reg.fixed_planes);
@@ -327,8 +328,7 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
    
    /* Shift so that lowest outcode bit is rightmost: 
     */
-   brw_MOV(p, c->reg.planemask, incoming);
-   brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(26));
+   brw_SHR(p, c->reg.planemask, incoming, brw_imm_ud(26));
 
    if (c->key.nr_userclip) {
       struct brw_reg tmp = retype(vec1(get_tmp(c)), BRW_REGISTER_TYPE_UD);
@@ -342,13 +342,5 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
       
       release_tmp(c, tmp);
    }
-
-   /* Test for -ve rhw workaround 
-    */
-   brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
-   brw_AND(p, vec1(brw_null_reg()), incoming, brw_imm_ud(1<<20));
-   brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f));
-   brw_set_predicate_control(p, BRW_PREDICATE_NONE);
-
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index e8f878a701..9bb7d2f703 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -240,6 +240,8 @@
 #define BRW_FRONTWINDING_CW      0
 #define BRW_FRONTWINDING_CCW     1
 
+#define BRW_SPRITE_POINT_ENABLE  16
+
 #define BRW_INDEX_BYTE     0
 #define BRW_INDEX_WORD     1
 #define BRW_INDEX_DWORD    2
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 0c64d7e756..5ca9b2f549 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -331,6 +331,7 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx,
       else {
 	 /* Otherwise, explicitly do the cliprects at this point:
 	  */
+          GLuint nprims = 0;
 	 for (j = 0; j < brw->intel.numClipRects; j++) {
 	    brw_emit_cliprect(brw, &brw->intel.pClipRects[j]);
 
@@ -338,6 +339,11 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx,
 	     */
 	    for (i = 0; i < nr_prims; i++) {
 	       brw_emit_prim(brw, &prim[i]);   
+
+          if (++nprims == VBO_MAX_PRIM) {
+              intel_batchbuffer_flush(brw->intel.batch);
+              nprims = 0;
+          }
 	    }
 	 }
       }
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 6150cac4aa..dc289ca9ae 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -593,6 +593,28 @@ void brw_upload_indices( struct brw_context *brw,
 				 ib_size,
 				 index_buffer->ptr,
 				 bufferobj);
+   } else {
+       if (((1 << get_index_type(index_buffer->type)) - 1) & offset) {
+           struct gl_buffer_object *vbo;
+           GLuint voffset;
+           GLubyte *map = ctx->Driver.MapBuffer(ctx,
+                                                GL_ELEMENT_ARRAY_BUFFER_ARB,
+                                                GL_DYNAMIC_DRAW_ARB,
+                                                bufferobj);
+           map += offset;
+           get_space(brw, ib_size, &vbo, &voffset);
+           
+           ctx->Driver.BufferSubData(ctx,
+                                     GL_ELEMENT_ARRAY_BUFFER_ARB,
+                                     voffset,
+                                     ib_size,
+                                     map,
+                                     vbo);
+           ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER_ARB, bufferobj);
+
+           bufferobj = vbo;
+           offset = voffset;
+       }
    }
 
    /* Emit the indexbuffer packet:
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 752fe49bcb..f7b1d31810 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -29,15 +29,15 @@
   *   Keith Whitwell <keith@tungstengraphics.com>
   */
   
+#include "main/imports.h"
+#include "main/enums.h"
 #include "shader/prog_parameter.h"
+#include "shader/program.h"
+#include "tnl/tnl.h"
+
 #include "brw_context.h"
 #include "brw_aub.h"
 #include "brw_util.h"
-#include "program.h"
-#include "imports.h"
-#include "enums.h"
-#include "tnl/tnl.h"
-
 
 static void brwBindProgram( GLcontext *ctx,
 			    GLenum target, 
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c
index d5175399d6..738ceb0552 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -43,7 +43,7 @@
 #include "brw_sf.h"
 #include "brw_state.h"
 
-#define DO_SETUP_BITS ((1<<FRAG_ATTRIB_MAX)-1)
+#define DO_SETUP_BITS ((1<<(FRAG_ATTRIB_MAX)) - 1)
 
 static void compile_sf_prog( struct brw_context *brw,
 			     struct brw_sf_prog_key *key )
@@ -74,6 +74,11 @@ static void compile_sf_prog( struct brw_context *brw,
       if (c.key.attrs & (1<<i)) {
 	 c.attr_to_idx[i] = idx;
 	 c.idx_to_attr[idx] = i;
+	 if (i >= VERT_RESULT_TEX0 && i <= VERT_RESULT_TEX7) {
+		 c.point_attrs[i].CoordReplace = 
+			brw->attribs.Point->CoordReplace[i - VERT_RESULT_TEX0];
+	 } else
+		 c.point_attrs[i].CoordReplace = GL_FALSE;
 	 idx++;
       }
    
@@ -90,7 +95,10 @@ static void compile_sf_prog( struct brw_context *brw,
       break;
    case SF_POINTS:
       c.nr_verts = 1;
-      brw_emit_point_setup( &c );
+      if (key->do_point_sprite)
+	  brw_emit_point_sprite_setup( &c );
+      else
+	  brw_emit_point_setup( &c );
       break;
    case SF_UNFILLED_TRIS:
       c.nr_verts = 3;
@@ -162,7 +170,8 @@ static void upload_sf_prog( struct brw_context *brw )
       break;
    }
 
-
+   key.do_point_sprite = brw->attribs.Point->PointSprite;
+   key.SpriteOrigin = brw->attribs.Point->SpriteOrigin;
    /* _NEW_LIGHT */
    key.do_flat_shading = (brw->attribs.Light->ShadeModel == GL_FLAT);
    key.do_twoside_color = (brw->attribs.Light->Enabled && brw->attribs.Light->Model.TwoSide);
@@ -179,7 +188,7 @@ static void upload_sf_prog( struct brw_context *brw )
 
 const struct brw_tracked_state brw_sf_prog = {
    .dirty = {
-      .mesa  = (_NEW_LIGHT|_NEW_POLYGON),
+      .mesa  = (_NEW_LIGHT|_NEW_POLYGON|_NEW_POINT),
       .brw   = (BRW_NEW_REDUCED_PRIMITIVE),
       .cache = CACHE_NEW_VS_PROG
    },
diff --git a/src/mesa/drivers/dri/i965/brw_sf.h b/src/mesa/drivers/dri/i965/brw_sf.h
index fb72b84ba8..e8946511dd 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.h
+++ b/src/mesa/drivers/dri/i965/brw_sf.h
@@ -34,9 +34,9 @@
 #define BRW_SF_H
 
 
+#include "shader/program.h"
 #include "brw_context.h"
 #include "brw_eu.h"
-#include "program.h"
 
 
 #define SF_POINTS    0
@@ -50,9 +50,14 @@ struct brw_sf_prog_key {
    GLuint do_flat_shading:1;
    GLuint attrs:16;
    GLuint frontface_ccw:1;
-   GLuint pad:11;
+   GLuint do_point_sprite:1;
+   GLuint pad:10;
+   GLenum SpriteOrigin;
 };
 
+struct brw_sf_point_tex {
+	GLboolean CoordReplace;	
+};
 
 struct brw_sf_compile {
    struct brw_compile func;
@@ -94,12 +99,14 @@ struct brw_sf_compile {
 
    GLubyte attr_to_idx[VERT_RESULT_MAX];   
    GLubyte idx_to_attr[VERT_RESULT_MAX];   
+   struct brw_sf_point_tex point_attrs[VERT_RESULT_MAX];
 };
 
  
 void brw_emit_tri_setup( struct brw_sf_compile *c );
 void brw_emit_line_setup( struct brw_sf_compile *c );
 void brw_emit_point_setup( struct brw_sf_compile *c );
+void brw_emit_point_sprite_setup( struct brw_sf_compile *c );
 void brw_emit_anyprim_setup( struct brw_sf_compile *c );
 
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c b/src/mesa/drivers/dri/i965/brw_sf_emit.c
index cbaf018c44..5e86e428fa 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c
@@ -497,6 +497,86 @@ void brw_emit_line_setup( struct brw_sf_compile *c )
    } 
 }
 
+void brw_emit_point_sprite_setup( struct brw_sf_compile *c )
+{
+   struct brw_compile *p = &c->func;
+   GLuint i;
+
+   c->nr_verts = 1;
+   alloc_regs(c);
+   copy_z_inv_w(c);
+   for (i = 0; i < c->nr_setup_regs; i++)
+   {
+      struct brw_sf_point_tex *tex = &c->point_attrs[c->idx_to_attr[2*i]];
+      struct brw_reg a0 = offset(c->vert[0], i);
+      GLushort pc, pc_persp, pc_linear;
+      GLboolean last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear);
+            
+      if (pc_persp)
+      {				
+	  if (!tex->CoordReplace) {
+	      brw_set_predicate_control_flag_value(p, pc_persp);
+	      brw_MUL(p, a0, a0, c->inv_w[0]);
+	  }
+      }
+
+      if (tex->CoordReplace) {
+	  /* Caculate 1.0/PointWidth */
+	  brw_math(&c->func,
+		  c->tmp,
+		  BRW_MATH_FUNCTION_INV,
+		  BRW_MATH_SATURATE_NONE,
+		  0,
+		  c->dx0,
+		  BRW_MATH_DATA_SCALAR,
+		  BRW_MATH_PRECISION_FULL);
+
+	  if (c->key.SpriteOrigin == GL_UPPER_LEFT) {
+	   	brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]);
+		brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0));
+	  	brw_MUL(p, c->m2Cy, c->tmp, negate(c->inv_w[0]));
+		brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0));
+	  } else {
+	   	brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]);
+		brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0));
+	  	brw_MUL(p, c->m2Cy, c->tmp, c->inv_w[0]);
+		brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0));
+	  }
+      } else {
+	  brw_MOV(p, c->m1Cx, brw_imm_ud(0));
+	  brw_MOV(p, c->m2Cy, brw_imm_ud(0));
+      }
+
+      {
+	 brw_set_predicate_control_flag_value(p, pc); 
+	 if (tex->CoordReplace) {
+	     if (c->key.SpriteOrigin == GL_UPPER_LEFT) {
+		 brw_MUL(p, c->m3C0, c->inv_w[0], brw_imm_f(1.0));
+		 brw_MOV(p, vec1(suboffset(c->m3C0, 0)), brw_imm_f(0.0));
+	     }
+	     else
+		 brw_MOV(p, c->m3C0, brw_imm_f(0.0));
+	 } else {
+	 	brw_MOV(p, c->m3C0, a0); /* constant value */
+	 }
+
+	 /* Copy m0..m3 to URB. 
+	  */
+	 brw_urb_WRITE(p, 
+		       brw_null_reg(),
+		       0,
+		       brw_vec8_grf(0, 0),
+		       0, 	/* allocate */
+		       1,	/* used */
+		       4, 	/* msg len */
+		       0,	/* response len */
+		       last, 	/* eot */
+		       last, 	/* writes complete */
+		       i*4,	/* urb destination offset */
+		       BRW_URB_SWIZZLE_TRANSPOSE);
+      }
+   }
+}
 
 /* Points setup - several simplifications as all attributes are
  * constant across the face of the point (point sprites excluded!)
@@ -561,6 +641,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
    struct brw_compile *p = &c->func;
    struct brw_reg ip = brw_ip_reg();
    struct brw_reg payload_prim = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0);
+   struct brw_reg payload_attr = get_element_ud(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), 0); 
    struct brw_reg primmask;
    struct brw_instruction *jmp;
    struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
@@ -582,7 +663,9 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
 					       (1<<_3DPRIM_TRIFAN_NOSTIPPLE)));
    jmp = brw_JMPI(p, ip, ip, brw_imm_w(0));
    {
+      brw_push_insn_state(p); 
       brw_emit_tri_setup( c );
+      brw_pop_insn_state(p);
       /* note - thread killed in subroutine */
    }
    brw_land_fwd_jump(p, jmp);
@@ -596,11 +679,23 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
 					       (1<<_3DPRIM_LINESTRIP_CONT_BF)));
    jmp = brw_JMPI(p, ip, ip, brw_imm_w(0));
    {
+      brw_push_insn_state(p); 
       brw_emit_line_setup( c );
+      brw_pop_insn_state(p);
       /* note - thread killed in subroutine */
    }
    brw_land_fwd_jump(p, jmp); 
 
+   brw_set_conditionalmod(p, BRW_CONDITIONAL_Z);
+   brw_AND(p, v1_null_ud, payload_attr, brw_imm_ud(1<<BRW_SPRITE_POINT_ENABLE));
+   jmp = brw_JMPI(p, ip, ip, brw_imm_w(0));
+   {
+      brw_push_insn_state(p); 
+      brw_emit_point_sprite_setup( c );
+      brw_pop_insn_state(p);
+   }
+   brw_land_fwd_jump(p, jmp); 
+
    brw_emit_point_setup( c );
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index bfac52d765..236c6fd42a 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -173,7 +173,8 @@ static void upload_sf_unit( struct brw_context *brw )
       
 
    /* _NEW_LINE */
-   sf.sf6.line_width = brw->attribs.Line->_Width * (1<<1);
+   /* XXX use ctx->Const.Min/MaxLineWidth here */
+   sf.sf6.line_width = CLAMP(brw->attribs.Line->Width, 1.0, 5.0) * (1<<1);
 
    sf.sf6.line_endcap_aa_region_width = 1;
    if (brw->attribs.Line->SmoothFlag)
@@ -183,7 +184,10 @@ static void upload_sf_unit( struct brw_context *brw )
 
    /* _NEW_POINT */
    sf.sf6.point_rast_rule = 1;	/* opengl conventions */
-   sf.sf7.point_size = brw->attribs.Point->_Size * (1<<3);
+   /* XXX clamp max depends on AA vs. non-AA */
+
+   sf.sf7.sprite_point = brw->attribs.Point->PointSprite;
+   sf.sf7.point_size = CLAMP(brw->attribs.Point->Size, 1.0, 255.0) * (1<<3);
    sf.sf7.use_point_size_state = !brw->attribs.Point->_Attenuated;
       
    /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
diff --git a/src/mesa/drivers/dri/i965/brw_tex.c b/src/mesa/drivers/dri/i965/brw_tex.c
index 9d4b9867d2..ad29316a42 100644
--- a/src/mesa/drivers/dri/i965/brw_tex.c
+++ b/src/mesa/drivers/dri/i965/brw_tex.c
@@ -154,13 +154,19 @@ brwChooseTextureFormat( GLcontext *ctx, GLint internalFormat,
 
    case GL_RGB_S3TC:
    case GL_RGB4_S3TC:
+   case GL_COMPRESSED_RGB_S3TC_DXT1_EXT:
+       return &_mesa_texformat_rgb_dxt1;
+
+   case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT:
+       return &_mesa_texformat_rgba_dxt1;
+
    case GL_RGBA_S3TC:
    case GL_RGBA4_S3TC:
    case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT:
+       return &_mesa_texformat_rgba_dxt3;
+
    case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT:
-   case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT:
-   case GL_COMPRESSED_RGB_S3TC_DXT1_EXT:
-     return &_mesa_texformat_rgb_dxt1; /* there is no rgba support? */
+       return &_mesa_texformat_rgba_dxt5;
 
    case GL_DEPTH_COMPONENT:
    case GL_DEPTH_COMPONENT16:
@@ -168,6 +174,25 @@ brwChooseTextureFormat( GLcontext *ctx, GLint internalFormat,
    case GL_DEPTH_COMPONENT32:
       return &_mesa_texformat_z16;
 
+   case GL_SRGB_EXT:
+   case GL_SRGB8_EXT:
+   case GL_SRGB_ALPHA_EXT:
+   case GL_SRGB8_ALPHA8_EXT:
+   case GL_SLUMINANCE_EXT:
+   case GL_SLUMINANCE8_EXT:
+   case GL_SLUMINANCE_ALPHA_EXT:
+   case GL_SLUMINANCE8_ALPHA8_EXT:
+   case GL_COMPRESSED_SRGB_EXT:
+   case GL_COMPRESSED_SRGB_ALPHA_EXT:
+   case GL_COMPRESSED_SLUMINANCE_EXT:
+   case GL_COMPRESSED_SLUMINANCE_ALPHA_EXT:
+	return &_mesa_texformat_srgba8;
+   case GL_COMPRESSED_SRGB_S3TC_DXT1_EXT:
+   case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT:
+   case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT3_EXT:
+   case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT5_EXT:
+     return &_mesa_texformat_srgb_dxt1;
+
    default:
       fprintf(stderr, "unexpected texture format %s in %s\n", 
 	      _mesa_lookup_enum_by_nr(internalFormat),
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index af1ad0f1ef..2094a1c8ad 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -37,6 +37,7 @@
 #include "intel_tex_layout.h"
 #include "macros.h"
 
+#define ALIGN(value, alignment)  ((value + alignment - 1) & ~(alignment - 1))
 
 GLboolean brw_miptree_layout( struct intel_mipmap_tree *mt )
 {
@@ -53,11 +54,20 @@ GLboolean brw_miptree_layout( struct intel_mipmap_tree *mt )
       GLuint pack_x_pitch, pack_x_nr;
       GLuint pack_y_pitch;
       GLuint level;
+      GLuint align_h = 2;
+      GLuint align_w = 4;
 
-      mt->pitch = ((mt->width0 * mt->cpp + 3) & ~3) / mt->cpp;
       mt->total_height = 0;
+      
+      if (mt->compressed) {
+          align_w = intel_compressed_alignment(mt->internal_format);
+          mt->pitch = ALIGN(width, align_w);
+          pack_y_pitch = (height + 3) / 4;
+      } else {
+          mt->pitch = ((mt->width0 * mt->cpp + 3) & ~3) / mt->cpp;
+          pack_y_pitch = ALIGN(mt->height0, align_h);
+      }
 
-      pack_y_pitch = MAX2(mt->height0, 2);
       pack_x_pitch = mt->pitch;
       pack_x_nr = 1;
 
@@ -83,20 +93,30 @@ GLboolean brw_miptree_layout( struct intel_mipmap_tree *mt )
 
 
 	 mt->total_height += y;
-
-	 if (pack_x_pitch > 4) {
-	    pack_x_pitch >>= 1;
-	    pack_x_nr <<= 1;
-	    assert(pack_x_pitch * pack_x_nr <= mt->pitch);
-	 }
-
-	 if (pack_y_pitch > 2) {
-	    pack_y_pitch >>= 1;
-	 }
-
 	 width  = minify(width);
 	 height = minify(height);
 	 depth  = minify(depth);
+
+    if (mt->compressed) {
+        pack_y_pitch = (height + 3) / 4;
+        
+        if (pack_x_pitch > ALIGN(width, align_w)) {
+            pack_x_pitch = ALIGN(width, align_w);
+            pack_x_nr <<= 1;
+        }
+    } else {
+        if (pack_x_pitch > 4) {
+            pack_x_pitch >>= 1;
+            pack_x_nr <<= 1;
+            assert(pack_x_pitch * pack_x_nr <= mt->pitch);
+        }
+
+        if (pack_y_pitch > 2) {
+            pack_y_pitch >>= 1;
+            pack_y_pitch = ALIGN(pack_y_pitch, align_h);
+        }
+    }
+
       }
       break;
    }
diff --git a/src/mesa/drivers/dri/i965/brw_vs.h b/src/mesa/drivers/dri/i965/brw_vs.h
index fdb5785d67..8843f816f9 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.h
+++ b/src/mesa/drivers/dri/i965/brw_vs.h
@@ -36,7 +36,7 @@
 
 #include "brw_context.h"
 #include "brw_eu.h"
-#include "program.h"
+#include "shader/program.h"
 
 
 struct brw_vs_prog_key {
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 6eb11b19ad..8733b470c2 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -30,8 +30,8 @@
   */
             
 
-#include "program.h"
-#include "macros.h"
+#include "main/macros.h"
+#include "shader/program.h"
 #include "shader/prog_parameter.h"
 #include "shader/prog_print.h"
 #include "brw_context.h"
@@ -201,7 +201,7 @@ static void unalias2( struct brw_vs_compile *c,
 				    struct brw_reg,
 				    struct brw_reg ))
 {
-   if ((dst.file == arg0.file && dst.nr == arg0.nr) &&
+   if ((dst.file == arg0.file && dst.nr == arg0.nr) ||
        (dst.file == arg1.file && dst.nr == arg1.nr)) {
       struct brw_compile *p = &c->func;
       struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask);
diff --git a/src/mesa/drivers/dri/i965/brw_vs_tnl.c b/src/mesa/drivers/dri/i965/brw_vs_tnl.c
index b69be350a9..2ed80dc36e 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_tnl.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_tnl.c
@@ -1000,13 +1000,19 @@ static void build_lighting( struct tnl_program *p )
 					       STATE_POSITION); 
 	    struct ureg V = get_eye_position(p);
 	    struct ureg dist = get_temp(p);
+       struct ureg tmpPpli = get_temp(p);
 
 	    VPpli = get_temp(p); 
 	    half = get_temp(p);
+
+       /* In homogeneous object coordinates
+        */
+       emit_op1(p, OPCODE_RCP, dist, 0, swizzle1(Ppli, W));
+       emit_op2(p, OPCODE_MUL, tmpPpli, 0, Ppli, dist);
  
 	    /* Calulate VPpli vector
 	     */
-	    emit_op2(p, OPCODE_SUB, VPpli, 0, Ppli, V); 
+	    emit_op2(p, OPCODE_SUB, VPpli, 0, tmpPpli, V); 
 
 	    /* Normalize VPpli.  The dist value also used in
 	     * attenuation below.
@@ -1038,6 +1044,7 @@ static void build_lighting( struct tnl_program *p )
 	    emit_normalize_vec3(p, half, half);
 
 	    release_temp(p, dist);
+       release_temp(p, tmpPpli);
 	 }
 
 	 /* Calculate dot products:
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 1497dc7968..904c00bef8 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -285,7 +285,7 @@ static void brw_wm_populate_key( struct brw_context *brw,
 
 
    /* BRW_NEW_WM_INPUT_DIMENSIONS */
-   key->projtex_mask = brw->wm.input_size_masks[4-1]; 
+   key->projtex_mask = brw->wm.input_size_masks[4-1] >> (FRAG_ATTRIB_TEX0 - FRAG_ATTRIB_WPOS); 
 
    /* _NEW_LIGHT */
    key->flat_shade = (brw->attribs.Light->ShadeModel == GL_FLAT);
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index f5fddfdb68..6dcf4732a9 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -34,9 +34,9 @@
 #define BRW_WM_H
 
 
+#include "shader/prog_instruction.h"
 #include "brw_context.h"
 #include "brw_eu.h"
-#include "prog_instruction.h"
 
 /* A big lookup table is used to figure out which and how many
  * additional regs will inserted before the main payload in the WM
diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c
index ff97d87dc4..62bb081206 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_fp.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c
@@ -660,7 +660,7 @@ static GLboolean projtex( struct brw_wm_compile *c,
       return 0;  /* ut2004 gun rendering !?! */
    else if (src.File == PROGRAM_INPUT && 
 	    GET_SWZ(src.Swizzle, W) == W &&
-	    (c->key.projtex_mask & (1<<src.Index)) == 0)
+           (c->key.projtex_mask & (1<<(src.Index + FRAG_ATTRIB_WPOS - FRAG_ATTRIB_TEX0))) == 0)
       return 0;
    else
       return 1;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index 93d4cfc3a5..3c0952acf0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -54,7 +54,7 @@ static GLuint translate_wrap_mode( GLenum wrap )
    case GL_REPEAT: 
       return BRW_TEXCOORDMODE_WRAP;
    case GL_CLAMP:  
-      return BRW_TEXCOORDMODE_CLAMP_BORDER; /* conform likes it this way */
+      return BRW_TEXCOORDMODE_CLAMP;
    case GL_CLAMP_TO_EDGE: 
       return BRW_TEXCOORDMODE_CLAMP; /* conform likes it this way */
    case GL_CLAMP_TO_BORDER: 
@@ -173,12 +173,12 @@ static void brw_update_sampler_state( struct gl_texture_unit *texUnit,
        * message (sample_c).  So need to recompile WM program when
        * shadow comparison is enabled on each/any texture unit.
        */
-      sampler->ss0.shadow_function = intel_translate_compare_func(texObj->CompareFunc);
+      sampler->ss0.shadow_function = intel_translate_shadow_compare_func(texObj->CompareFunc);
    }
 
    /* Set LOD bias: 
     */
-   sampler->ss0.lod_bias = S_FIXED(texUnit->LodBias + texObj->LodBias, 6);
+   sampler->ss0.lod_bias = S_FIXED(CLAMP(texUnit->LodBias + texObj->LodBias, -16, 15), 6);
 
    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
@@ -192,8 +192,8 @@ static void brw_update_sampler_state( struct gl_texture_unit *texUnit,
     */
    sampler->ss0.base_level = U_FIXED(0, 1);
 
-   sampler->ss1.max_lod = U_FIXED(MAX2(texObj->MaxLod, 0), 6);
-   sampler->ss1.min_lod = U_FIXED(MAX2(texObj->MinLod, 0), 6);
+   sampler->ss1.max_lod = U_FIXED(MIN2(MAX2(texObj->MaxLod, 0), 13), 6);
+   sampler->ss1.min_lod = U_FIXED(MIN2(MAX2(texObj->MinLod, 0), 13), 6);
    
    sampler->ss2.default_color_pointer = sdc_gs_offset >> 5;
 }
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index ff5cb31bdd..5b4f2abd0e 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -117,7 +117,7 @@ static void upload_wm_unit(struct brw_context *brw )
    wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 
    /* CACHE_NEW_SAMPLER */
-   wm.wm4.sampler_count = brw->wm.sampler_count;
+   wm.wm4.sampler_count = (brw->wm.sampler_count + 1) / 4;
    wm.wm4.sampler_state_pointer = brw->wm.sampler_gs_offset >> 5;
 
    /* BRW_NEW_FRAGMENT_PROGRAM */
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index d24c618a66..0a45164a0f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -114,11 +114,24 @@ static GLuint translate_tex_format( GLuint mesa_format )
       return BRW_SURFACEFORMAT_FXT1;
 
    case MESA_FORMAT_Z16:
-      return BRW_SURFACEFORMAT_L16_UNORM;
+      return BRW_SURFACEFORMAT_I16_UNORM;
 
-   case MESA_FORMAT_RGBA_DXT1:
    case MESA_FORMAT_RGB_DXT1:
-      return BRW_SURFACEFORMAT_DXT1_RGB;
+       return BRW_SURFACEFORMAT_DXT1_RGB;
+
+   case MESA_FORMAT_RGBA_DXT1:
+       return BRW_SURFACEFORMAT_BC1_UNORM;
+       
+   case MESA_FORMAT_RGBA_DXT3:
+       return BRW_SURFACEFORMAT_BC2_UNORM;
+       
+   case MESA_FORMAT_RGBA_DXT5:
+       return BRW_SURFACEFORMAT_BC3_UNORM;
+
+   case MESA_FORMAT_SRGBA8:
+      return BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB;
+   case MESA_FORMAT_SRGB_DXT1:
+      return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
 
    default:
       assert(0);
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 173d1d5b6c..f88cbb2328 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -532,12 +532,15 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
 				  GLuint dst_offset,
 				  GLboolean dst_tiled,
 				  GLshort x, GLshort y, 
-				  GLshort w, GLshort h)
+				  GLshort w, GLshort h,
+				  GLenum logic_op)
 {
    struct xy_setup_blit setup;
    struct xy_text_immediate_blit text;
    int dwords = ((src_size + 7) & ~7) / 4;
 
+   assert( logic_op - GL_CLEAR >= 0 );
+   assert( logic_op - GL_CLEAR < 0x10 );
 
    if (w < 0 || h < 0) 
       return;
@@ -561,7 +564,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
    setup.br0.length = (sizeof(setup) / sizeof(int)) - 2;
       
    setup.br13.dest_pitch = dst_pitch;
-   setup.br13.rop = 0xcc;
+   setup.br13.rop = translate_raster_op(logic_op);
    setup.br13.color_depth = (cpp == 4) ? BR13_8888 : BR13_565;
    setup.br13.clipping_enable = 0;
    setup.br13.mono_source_transparency = 1;
diff --git a/src/mesa/drivers/dri/i965/intel_blit.h b/src/mesa/drivers/dri/i965/intel_blit.h
index 8b0cc65243..e361545c8f 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.h
+++ b/src/mesa/drivers/dri/i965/intel_blit.h
@@ -72,6 +72,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
 				  GLuint dst_offset,
 				  GLboolean dst_tiled,
 				  GLshort dst_x, GLshort dst_y, 
-				  GLshort w, GLshort h);
+				  GLshort w, GLshort h,
+				  GLenum logic_op );
 
 #endif
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 9617cbebbf..4a95087d78 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -66,6 +66,7 @@
 int INTEL_DEBUG = (0);
 #endif
 
+#define need_GL_NV_point_sprite
 #define need_GL_ARB_multisample
 #define need_GL_ARB_point_parameters
 #define need_GL_ARB_texture_compression
@@ -81,6 +82,7 @@ int INTEL_DEBUG = (0);
 #define need_GL_EXT_fog_coord
 #define need_GL_EXT_multi_draw_arrays
 #define need_GL_EXT_secondary_color
+#define need_GL_EXT_point_parameters
 #include "extension_helper.h"
 
 #ifndef VERBOSE
@@ -146,6 +148,7 @@ const struct dri_extension card_extensions[] =
     { "GL_ARB_multisample",                GL_ARB_multisample_functions },
     { "GL_ARB_multitexture",               NULL },
     { "GL_ARB_point_parameters",           GL_ARB_point_parameters_functions },
+    { "GL_NV_point_sprite",                GL_NV_point_sprite_functions },
     { "GL_ARB_texture_border_clamp",       NULL },
     { "GL_ARB_texture_compression",        GL_ARB_texture_compression_functions },
     { "GL_ARB_texture_cube_map",           NULL },
@@ -158,6 +161,8 @@ const struct dri_extension card_extensions[] =
     { "GL_NV_texture_rectangle",           NULL },
     { "GL_EXT_texture_rectangle",          NULL },
     { "GL_ARB_texture_rectangle",          NULL },
+    { "GL_ARB_point_sprite",               NULL},
+    { "GL_ARB_point_parameters",	   NULL }, 
     { "GL_ARB_vertex_buffer_object",       GL_ARB_vertex_buffer_object_functions },
     { "GL_ARB_vertex_program",             GL_ARB_vertex_program_functions },
     { "GL_ARB_window_pos",                 GL_ARB_window_pos_functions },
@@ -177,6 +182,7 @@ const struct dri_extension card_extensions[] =
     { "GL_EXT_texture_env_dot3",           NULL },
     { "GL_EXT_texture_filter_anisotropic", NULL },
     { "GL_EXT_texture_lod_bias",           NULL },
+    { "GL_EXT_texture_sRGB",               NULL },
     { "GL_3DFX_texture_compression_FXT1",  NULL },
     { "GL_APPLE_client_storage",           NULL },
     { "GL_MESA_pack_invert",               NULL },
@@ -570,6 +576,10 @@ GLboolean intelMakeCurrent(__DRIcontextPrivate *driContextPriv,
    if (driContextPriv) {
       struct intel_context *intel = (struct intel_context *) driContextPriv->driverPrivate;
 
+      if (intel->driReadDrawable != driReadPriv) {
+          intel->driReadDrawable = driReadPriv;
+      }
+
       if ( intel->driDrawable != driDrawPriv ) {
 	 /* Shouldn't the readbuffer be stored also? */
 	 driDrawableInitVBlank( driDrawPriv, intel->vblank_flags,
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 406f8483dc..053d93a82b 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -234,6 +234,7 @@ struct intel_context
    int driFd;
 
    __DRIdrawablePrivate *driDrawable;
+   __DRIdrawablePrivate *driReadDrawable;
    __DRIscreenPrivate *driScreen;
    intelScreenPrivate *intelScreen; 
    volatile drmI830Sarea *sarea; 
@@ -463,7 +464,7 @@ extern void intelInitStateFuncs( struct dd_function_table *functions );
 #define BLENDFACT_INV_CONST_ALPHA	0x0f
 #define BLENDFACT_MASK          	0x0f
 
-
+extern int intel_translate_shadow_compare_func( GLenum func );
 extern int intel_translate_compare_func( GLenum func );
 extern int intel_translate_stencil_op( GLenum op );
 extern int intel_translate_blend_factor( GLenum factor );
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 8486086b27..0fb33e27f4 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -75,7 +75,7 @@ struct intel_mipmap_tree *intel_miptree_create( struct intel_context *intel,
    mt->width0 = width0;
    mt->height0 = height0;
    mt->depth0 = depth0;
-   mt->cpp = compressed ? 2 : cpp;
+   mt->cpp = cpp;
    mt->compressed = compressed;
 
    switch (intel->intelScreen->deviceID) {
@@ -211,7 +211,7 @@ GLuint intel_miptree_image_offset(struct intel_mipmap_tree *mt,
 
 
 
-
+extern GLuint intel_compressed_alignment(GLenum);
 /* Upload data for a particular image.
  */
 GLboolean intel_miptree_image_data(struct intel_context *intel, 
@@ -226,6 +226,17 @@ GLboolean intel_miptree_image_data(struct intel_context *intel,
    GLuint dst_offset = intel_miptree_image_offset(dst, face, level);
    const GLuint *dst_depth_offset = intel_miptree_depth_offsets(dst, level);
    GLuint i;
+   GLuint width, height, alignment;
+
+   width = dst->level[level].width;
+   height = dst->level[level].height;
+
+   if (dst->compressed) {
+       alignment = intel_compressed_alignment(dst->internal_format);
+       src_row_pitch = ((src_row_pitch + alignment - 1) & ~(alignment - 1));
+       width = ((width + alignment - 1) & ~(alignment - 1));
+       height = (height + 3) / 4;
+   }
 
    DBG("%s\n", __FUNCTION__);
    for (i = 0; i < depth; i++) {
@@ -237,8 +248,8 @@ GLboolean intel_miptree_image_data(struct intel_context *intel,
 			     src,
 			     src_row_pitch,
 			     0, 0,	/* source x,y */
-			     dst->level[level].width,
-			     dst->level[level].height))
+			     width,
+			     height))
 	 return GL_FALSE;
       src += src_image_pitch;
    }
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
index 5841afaa3e..79c1fee9c0 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
@@ -168,12 +168,15 @@ do_blit_bitmap( GLcontext *ctx,
 {
    struct intel_context *intel = intel_context(ctx);
    struct intel_region *dst = intel_drawbuf_region(intel);
-   
+   GLfloat tmpColor[4];
+
    union {
       GLuint ui;
       GLubyte ub[4];
    } color;
 
+   if (!dst)
+       return GL_FALSE;
 
    if (unpack->BufferObj->Name) {
       bitmap = map_pbo(ctx, width, height, unpack, bitmap);
@@ -181,10 +184,16 @@ do_blit_bitmap( GLcontext *ctx,
 	 return GL_TRUE;	/* even though this is an error, we're done */
    }
 
-   UNCLAMPED_FLOAT_TO_CHAN(color.ub[0], ctx->Current.RasterColor[2]);
-   UNCLAMPED_FLOAT_TO_CHAN(color.ub[1], ctx->Current.RasterColor[1]);
-   UNCLAMPED_FLOAT_TO_CHAN(color.ub[2], ctx->Current.RasterColor[0]);
-   UNCLAMPED_FLOAT_TO_CHAN(color.ub[3], ctx->Current.RasterColor[3]);
+   COPY_4V(tmpColor, ctx->Current.RasterColor);
+
+   if (NEED_SECONDARY_COLOR(ctx)) {
+       ADD_3V(tmpColor, tmpColor, ctx->Current.RasterSecondaryColor);
+   }
+
+   UNCLAMPED_FLOAT_TO_CHAN(color.ub[0], tmpColor[2]);
+   UNCLAMPED_FLOAT_TO_CHAN(color.ub[1], tmpColor[1]);
+   UNCLAMPED_FLOAT_TO_CHAN(color.ub[2], tmpColor[0]);
+   UNCLAMPED_FLOAT_TO_CHAN(color.ub[3], tmpColor[3]);
 
    /* Does zoom apply to bitmaps?
     */
@@ -226,10 +235,10 @@ do_blit_bitmap( GLcontext *ctx,
       dsty = dPriv->y + (dPriv->h - dsty - height);  
       dstx = dPriv->x + dstx;
 
-      dest_rect.x1 = dstx;
-      dest_rect.y1 = dsty;
-      dest_rect.x2 = dstx + width;
-      dest_rect.y2 = dsty + height;
+      dest_rect.x1 = dstx < 0 ? 0 : dstx;
+      dest_rect.y1 = dsty < 0 ? 0 : dsty;
+      dest_rect.x2 = dstx + width < 0 ? 0 : dstx + width;
+      dest_rect.y2 = dsty + height < 0 ? 0 : dsty + height;
 
       for (i = 0; i < nbox; i++) {
          drm_clip_rect_t rect;
@@ -260,7 +269,9 @@ do_blit_bitmap( GLcontext *ctx,
 	       int h = MIN2(DY, box_h - py);
 	       int w = MIN2(DX, box_w - px); 
 	       GLuint sz = align(align(w,8) * h, 64)/8;
-	    
+	       GLenum logic_op = ctx->Color.ColorLogicOpEnabled ?
+		  ctx->Color.LogicOp : GL_COPY;
+
 	       assert(sz <= sizeof(stipple));
 	       memset(stipple, 0, sz);
 
@@ -288,7 +299,8 @@ do_blit_bitmap( GLcontext *ctx,
 						  dst->tiled,
 						  rect.x1 + px,
 						  rect.y2 - (py + h),
-						  w, h);
+						  w, h,
+						  logic_op);
 	    } 
 	 } 
       }
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_copy.c b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
index 58dc49505f..3bdf2fb479 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_copy.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
@@ -231,6 +231,7 @@ do_blit_copypixels(GLcontext * ctx,
 
    if (intel->driDrawable->numClipRects) {
       __DRIdrawablePrivate *dPriv = intel->driDrawable;
+      __DRIdrawablePrivate *dReadPriv = intel->driReadDrawable;
       drm_clip_rect_t *box = dPriv->pClipRects;
       drm_clip_rect_t dest_rect;
       GLint nbox = dPriv->numClipRects;
@@ -262,8 +263,8 @@ do_blit_copypixels(GLcontext * ctx,
       srcy = dPriv->h - srcy - height;  
       dstx += dPriv->x;
       dsty += dPriv->y;
-      srcx += dPriv->x;
-      srcy += dPriv->y;
+      srcx += dReadPriv->x;
+      srcy += dReadPriv->y;
 
       /* Clip against the source region.  This is the only source
        * clipping we do.  Dst is clipped with cliprects below.
diff --git a/src/mesa/drivers/dri/i965/intel_state.c b/src/mesa/drivers/dri/i965/intel_state.c
index 2e442db619..2f5467a4e4 100644
--- a/src/mesa/drivers/dri/i965/intel_state.c
+++ b/src/mesa/drivers/dri/i965/intel_state.c
@@ -38,6 +38,31 @@
 #include "intel_regions.h"
 #include "swrast/swrast.h"
 
+int intel_translate_shadow_compare_func( GLenum func )
+{
+   switch(func) {
+   case GL_NEVER: 
+       return COMPAREFUNC_ALWAYS; 
+   case GL_LESS: 
+       return COMPAREFUNC_LEQUAL; 
+   case GL_LEQUAL: 
+       return COMPAREFUNC_LESS;
+   case GL_GREATER: 
+       return COMPAREFUNC_GEQUAL; 
+   case GL_GEQUAL: 
+      return COMPAREFUNC_GREATER; 
+   case GL_NOTEQUAL: 
+      return COMPAREFUNC_EQUAL; 
+   case GL_EQUAL: 
+      return COMPAREFUNC_NOTEQUAL; 
+   case GL_ALWAYS: 
+       return COMPAREFUNC_NEVER; 
+   }
+
+   fprintf(stderr, "Unknown value in %s: %x\n", __FUNCTION__, func);
+   return COMPAREFUNC_NEVER; 
+}
+
 int intel_translate_compare_func( GLenum func )
 {
    switch(func) {
diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index 44ee94614d..8c05e7cdab 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -122,6 +122,29 @@ static void intel_texture_invalidate_cb( struct intel_context *intel,
    intel_texture_invalidate( (struct intel_texture_object *) ptr );
 }
 
+#include "texformat.h"
+static GLuint intel_compressed_num_bytes(GLenum mesaFormat)
+{
+    GLuint bytes = 0;
+
+    switch (mesaFormat) {
+    case MESA_FORMAT_RGB_FXT1:
+    case MESA_FORMAT_RGBA_FXT1:
+    case MESA_FORMAT_RGB_DXT1:
+    case MESA_FORMAT_RGBA_DXT1:
+        bytes = 2;
+        break;
+
+    case MESA_FORMAT_RGBA_DXT3:
+    case MESA_FORMAT_RGBA_DXT5:
+        bytes = 4;
+    
+    default:
+        break;
+    }
+
+    return bytes;
+}
 
 /*  
  */
@@ -132,7 +155,8 @@ GLuint intel_finalize_mipmap_tree( struct intel_context *intel,
    GLuint face, i;
    GLuint nr_faces = 0;
    struct gl_texture_image *firstImage;
-
+   GLuint cpp = 0;
+   
    if( tObj == intel->frame_buffer_texobj )
       return GL_FALSE;
    
@@ -165,6 +189,12 @@ GLuint intel_finalize_mipmap_tree( struct intel_context *intel,
 
 
 
+   if (firstImage->IsCompressed) {
+       cpp = intel_compressed_num_bytes(firstImage->TexFormat->MesaFormat);
+   } else {
+       cpp = firstImage->TexFormat->TexelBytes;
+   }
+       
    /* Check tree can hold all active levels.  Check tree matches
     * target, imageFormat, etc.
     */
@@ -176,7 +206,7 @@ GLuint intel_finalize_mipmap_tree( struct intel_context *intel,
 	intelObj->mt->width0 != firstImage->Width ||
 	intelObj->mt->height0 != firstImage->Height ||
 	intelObj->mt->depth0 != firstImage->Depth ||
-	intelObj->mt->cpp != firstImage->TexFormat->TexelBytes ||
+	intelObj->mt->cpp != cpp ||
 	intelObj->mt->compressed != firstImage->IsCompressed)) 
    {
       intel_miptree_destroy(intel, intelObj->mt);
@@ -199,7 +229,7 @@ GLuint intel_finalize_mipmap_tree( struct intel_context *intel,
 					  firstImage->Width,
 					  firstImage->Height,
 					  firstImage->Depth,
-					  firstImage->TexFormat->TexelBytes,
+					  cpp,
 					  firstImage->IsCompressed);
 
       /* Tell the buffer manager that we will manage the backing