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authorEric Anholt <eric@anholt.net>2011-01-05 17:02:08 -0800
committerEric Anholt <eric@anholt.net>2011-01-05 18:23:54 -0800
commit7ce6517f3ac41bf770ab39aba4509d4f535ef663 (patch)
tree3563dc5da10a71f71981a0ceb5fdbd00b37a1f79 /src/mesa/drivers/dri/i965
parent01b70c06284f3a0ab2de61228b73c78ed00a1a14 (diff)
intel: Always allocate miptrees from level 0, not tObj->BaseLevel.
BaseLevel/MaxLevel are mostly used for two things: clamping texture access for FBO rendering, and limiting the used mipmap levels when incrementally loading textures. By restricting our mipmap trees to just the current BaseLevel/MaxLevel, we caused reallocation thrashing in the common case, for a theoretical win if someone really did want just levels 2..4 or whatever of their texture object. Bug #30366
Diffstat (limited to 'src/mesa/drivers/dri/i965')
-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c4
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_sampler_state.c11
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c10
3 files changed, 10 insertions, 15 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 9ac0713a1d..66adc49cc9 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -67,7 +67,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
i945_miptree_layout_2d(intel, mt, tiling, 6);
- for (level = mt->first_level; level <= mt->last_level; level++) {
+ for (level = 0; level < mt->levels; level++) {
for (q = 0; q < 6; q++) {
intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
}
@@ -101,7 +101,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
pack_x_pitch = width;
pack_x_nr = 1;
- for (level = mt->first_level ; level <= mt->last_level ; level++) {
+ for (level = 0; level < mt->levels; level++) {
GLuint nr_images = mt->target == GL_TEXTURE_3D ? depth : 6;
GLint x = 0;
GLint y = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index 30672b4251..f830e25626 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -115,6 +115,7 @@ struct wm_sampler_key {
struct wm_sampler_entry {
GLenum tex_target;
GLenum wrap_r, wrap_s, wrap_t;
+ uint32_t base_level;
float maxlod, minlod;
float lod_bias;
float max_aniso;
@@ -243,14 +244,7 @@ static void brw_update_sampler_state(struct brw_context *brw,
sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
- /* Set BaseMipLevel, MaxLOD, MinLOD:
- *
- * XXX: I don't think that using firstLevel, lastLevel works,
- * because we always setup the surface state as if firstLevel ==
- * level zero. Probably have to subtract firstLevel from each of
- * these:
- */
- sampler->ss0.base_level = U_FIXED(0, 1);
+ sampler->ss0.base_level = U_FIXED(key->base_level, 1);
sampler->ss1.max_lod = U_FIXED(CLAMP(key->maxlod, 0, 13), 6);
sampler->ss1.min_lod = U_FIXED(CLAMP(key->minlod, 0, 13), 6);
@@ -292,6 +286,7 @@ brw_wm_sampler_populate_key(struct brw_context *brw,
entry->wrap_s = texObj->WrapS;
entry->wrap_t = texObj->WrapT;
+ entry->base_level = texObj->BaseLevel;
entry->maxlod = texObj->MaxLod;
entry->minlod = texObj->MinLod;
entry->lod_bias = texUnit->LodBias + texObj->LodBias;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 3b59b0b98e..1769991306 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -181,15 +181,15 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
/* surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
surf.ss1.base_addr = intelObj->mt->region->buffer->offset; /* reloc */
+ /* mip_count is #levels - 1 */
surf.ss2.mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
- surf.ss2.width = firstImage->Width - 1;
- surf.ss2.height = firstImage->Height - 1;
+ surf.ss2.width = intelObj->mt->width0 - 1;
+ surf.ss2.height = intelObj->mt->height0 - 1;
brw_set_surface_tiling(&surf, intelObj->mt->region->tiling);
surf.ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1;
- surf.ss3.depth = firstImage->Depth - 1;
+ surf.ss3.depth = intelObj->mt->depth0 - 1;
+ surf.ss4.min_lod = tObj->BaseLevel;
- surf.ss4.min_lod = 0;
-
if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
surf.ss0.cube_pos_x = 1;
surf.ss0.cube_pos_y = 1;