[intel] Add more cliprect modes to cover other meanings for batch emits.

The previous change gave us only two modes, one which looped over the batch
per cliprect (3d drawing) and one that didn't (state updeast).
However, we really want 4:

- Batch doesn't care about cliprects (state updates)
- Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing)
- Batch needs to be executed just once (region fills, copies, etc.)
- Batch already includes cliprect handling, and must be flushed by unlock time
  (copybuffers, clears).

All callers should now be fixed to use one of these states for any batchbuffer
emits.  Thanks to Keith Whitwell for pointing out the failure.

10 files changed, 42 insertions, 16 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 8a71a4f500..9ddd41d3f3 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -656,6 +656,7 @@ void brw_debug_batch(struct intel_context *intel);
 void brwUpdateTextureState( struct intel_context *intel );
 void brw_FrameBufferTexInit( struct brw_context *brw );
 void brw_FrameBufferTexDestroy( struct brw_context *brw );
+void brw_validate_textures( struct brw_context *brw );
 
 /*======================================================================
  * brw_metaops.c
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 3841c0a9cd..2e39ec4805 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -201,7 +201,7 @@ static void upload_constant_buffer(struct brw_context *brw)
    brw->curbe.tracked_state.dirty.mesa |= fp->param_state;
 
    if (sz == 0) {
-      BEGIN_BATCH(2, INTEL_BATCH_NO_CLIPRECTS);
+      BEGIN_BATCH(2, IGNORE_CLIPRECTS);
       OUT_BATCH((CMD_CONST_BUFFER << 16) | (2 - 2));
       OUT_BATCH(0);
       ADVANCE_BATCH();
@@ -322,7 +322,7 @@ static void upload_constant_buffer(struct brw_context *brw)
     * flushes as necessary when doublebuffering of CURBEs isn't
     * possible.
     */
-   BEGIN_BATCH(2, INTEL_BATCH_NO_CLIPRECTS);
+   BEGIN_BATCH(2, IGNORE_CLIPRECTS);
    OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2));
    OUT_RELOC(brw->curbe.curbe_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
 	     (sz - 1));
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 887eebe475..c74aff785e 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -147,7 +147,7 @@ static void brw_emit_prim( struct brw_context *brw,
 
    if (prim_packet.verts_per_instance) {
       intel_batchbuffer_data( brw->intel.batch, &prim_packet,
-			      sizeof(prim_packet), INTEL_BATCH_CLIPRECTS);
+			      sizeof(prim_packet), LOOP_CLIPRECTS);
    }
 }
 
@@ -256,6 +256,8 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx,
    if (ctx->NewState)
       _mesa_update_state( ctx );
 
+   brw_validate_textures( brw );
+
    /* Bind all inputs, derive varying and size information:
     */
    brw_merge_inputs( brw, arrays );
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 8c4e1bd569..0df61f2972 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -538,7 +538,7 @@ GLboolean brw_upload_vertices( struct brw_context *brw,
    vbp.header.bits.length = (1 + nr_enabled * 4) - 2;
    vbp.header.bits.opcode = CMD_VERTEX_BUFFER;
 
-   BEGIN_BATCH(vbp.header.bits.length+2, 0);
+   BEGIN_BATCH(vbp.header.bits.length+2, IGNORE_CLIPRECTS);
    OUT_BATCH( vbp.header.dword );
    
    for (i = 0; i < nr_enabled; i++) {
@@ -625,7 +625,7 @@ void brw_upload_indices( struct brw_context *brw,
       ib.header.bits.cut_index_enable = 0;
    
 
-      BEGIN_BATCH(4, 0);
+      BEGIN_BATCH(4, IGNORE_CLIPRECTS);
       OUT_BATCH( ib.header.dword );
       OUT_RELOC( buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, offset);
       OUT_RELOC( buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index eefd22ecb2..acc19f7767 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -82,7 +82,7 @@ static void upload_binding_table_pointers(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
 
-   BEGIN_BATCH(6, INTEL_BATCH_NO_CLIPRECTS);
+   BEGIN_BATCH(6, IGNORE_CLIPRECTS);
    OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 | (6 - 2));
    OUT_BATCH(0); /* vs */
    OUT_BATCH(0); /* gs */
@@ -112,7 +112,7 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
 {
    struct intel_context *intel = &brw->intel;
 
-   BEGIN_BATCH(7, INTEL_BATCH_NO_CLIPRECTS);
+   BEGIN_BATCH(7, IGNORE_CLIPRECTS);
    OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
    OUT_RELOC(brw->vs.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
    if (brw->gs.prog_active)
@@ -184,7 +184,7 @@ static void upload_depthbuffer(struct brw_context *brw)
    struct intel_region *region = brw->state.depth_region;
 
    if (region == NULL) {
-      BEGIN_BATCH(5, INTEL_BATCH_NO_CLIPRECTS);
+      BEGIN_BATCH(5, IGNORE_CLIPRECTS);
       OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (5 - 2));
       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 		(BRW_SURFACE_NULL << 29));
@@ -210,7 +210,7 @@ static void upload_depthbuffer(struct brw_context *brw)
 	 return;
       }
 
-      BEGIN_BATCH(5, INTEL_BATCH_NO_CLIPRECTS);
+      BEGIN_BATCH(5, IGNORE_CLIPRECTS);
       OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (5 - 2));
       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 		(format << 18) |
@@ -445,7 +445,7 @@ static void upload_state_base_address( struct brw_context *brw )
    /* Output the structure (brw_state_base_address) directly to the
     * batchbuffer, so we can emit relocations inline.
     */
-   BEGIN_BATCH(6, INTEL_BATCH_NO_CLIPRECTS);
+   BEGIN_BATCH(6, IGNORE_CLIPRECTS);
    OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
    OUT_BATCH(1); /* General state base address */
    OUT_BATCH(1); /* Surface state base address */
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index e4bb39811a..66755cabaf 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -122,7 +122,7 @@ void brw_destroy_cache( struct brw_context *brw );
 /***********************************************************************
  * brw_state_batch.c
  */
-#define BRW_BATCH_STRUCT(brw, s) intel_batchbuffer_data( brw->intel.batch, (s), sizeof(*(s)), 0)
+#define BRW_BATCH_STRUCT(brw, s) intel_batchbuffer_data( brw->intel.batch, (s), sizeof(*(s)), IGNORE_CLIPRECTS)
 #define BRW_CACHED_BATCH_STRUCT(brw, s) brw_cached_batch_struct( brw, (s), sizeof(*(s)) )
 
 GLboolean brw_cached_batch_struct( struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 34be101273..77e2736d11 100644
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -48,7 +48,7 @@ GLboolean brw_cached_batch_struct( struct brw_context *brw,
    struct header *newheader = (struct header *)data;
 
    if (brw->emit_state_always) {
-      intel_batchbuffer_data(brw->intel.batch, data, sz, 0);
+      intel_batchbuffer_data(brw->intel.batch, data, sz, IGNORE_CLIPRECTS);
       return GL_TRUE;
    }
 
@@ -75,7 +75,7 @@ GLboolean brw_cached_batch_struct( struct brw_context *brw,
 
  emit:
    memcpy(item->header, newheader, sz);
-   intel_batchbuffer_data(brw->intel.batch, data, sz, 0);
+   intel_batchbuffer_data(brw->intel.batch, data, sz, IGNORE_CLIPRECTS);
    return GL_TRUE;
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_tex.c b/src/mesa/drivers/dri/i965/brw_tex.c
index b344dd7d27..05f724cc23 100644
--- a/src/mesa/drivers/dri/i965/brw_tex.c
+++ b/src/mesa/drivers/dri/i965/brw_tex.c
@@ -44,6 +44,7 @@
 #include "intel_context.h"
 #include "intel_ioctl.h"
 #include "intel_regions.h"
+#include "intel_tex.h"
 #include "brw_context.h"
 #include "brw_defines.h"
 
@@ -76,3 +77,21 @@ void brw_FrameBufferTexDestroy( struct brw_context *brw )
    brw->intel.ctx.Driver.DeleteTexture( &brw->intel.ctx,
 					brw->intel.frame_buffer_texobj );
 }
+
+/**
+ * Finalizes all textures, completing any rendering that needs to be done
+ * to prepare them.
+ */
+void brw_validate_textures( struct brw_context *brw )
+{
+   struct intel_context *intel = &brw->intel;
+   int i;
+
+   for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
+      struct gl_texture_unit *texUnit = &brw->attribs.Texture->Unit[i];
+
+      if (texUnit->_ReallyEnabled) {
+	 intel_finalize_mipmap_tree(intel, i);
+      }
+   }
+}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index cf253391b5..7bb8e4d118 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -394,9 +394,7 @@ static void upload_wm_surfaces(struct brw_context *brw )
 
       /* _NEW_TEXTURE, BRW_NEW_TEXDATA 
        */
-      if (texUnit->_ReallyEnabled &&
-	  intel_finalize_mipmap_tree(intel, i))
-      {
+      if (texUnit->_ReallyEnabled) {
 	 brw_update_texture_surface(ctx, i);
 	 brw->wm.nr_surfaces = i+2;
       }
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 973eed50f9..e54005af27 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -812,6 +812,12 @@ void UNLOCK_HARDWARE( struct intel_context *intel )
 
    DRM_UNLOCK(intel->driFd, intel->driHwLock, intel->hHWContext);
    _glthread_UNLOCK_MUTEX(lockMutex); 
+
+   /**
+    * Nothing should be left in batch outside of LOCK/UNLOCK which references
+    * cliprects.
+    */
+   assert(intel->batch->cliprect_mode != REFERENCES_CLIPRECTS);
 }