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| author | Eric Anholt <eric@anholt.net> | 2009-01-29 14:57:49 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-01-30 13:46:37 -0800 |
| commit | 3ee21f30cda27e0ee1357f930163526622ba9434 (patch) | |
| tree | b12c19ea07993dd954ed0689a421e9718943a0b0 /src/mesa/drivers/dri/intel/intel_buffers.c | |
| parent | bc968e515dff20fc3cbcd01066886ba66f707a1b (diff) | |
intel: Expose more FBconfigs in the 3D driver.
We can support any combination of (a8r8g8b8, x8r8g8b8, r5g6b5) x (z0,z24,z24s8)
on either class of chipsets. The only restriction is no mixing bpp when also
mixing tiling. This shouldn't be occurring currently.
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_buffers.c')
0 files changed, 0 insertions, 0 deletions