[965] Move to using shared texture management code.

This removes the delayed texture upload optimization from 965, in exchange for
bringing us closer to PBO support.  It also disables SGIS_generate_mipmap,
which didn't seem to be working before anyway, according to the lodbias demo.

1 files changed, 8 insertions, 18 deletions

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index df7b3d378c..4d36fc0025 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -78,28 +78,17 @@ intel_miptree_create(struct intel_context *intel,
    mt->compressed = compress_byte ? 1 : 0;
    mt->refcount = 1; 
 
-   switch (intel->intelScreen->deviceID) {
-   case PCI_CHIP_I945_G:
-   case PCI_CHIP_I945_GM:
-   case PCI_CHIP_I945_GME:
-   case PCI_CHIP_G33_G:
-   case PCI_CHIP_Q33_G:
-   case PCI_CHIP_Q35_G:
+#ifdef I915
+   if (IS_945(intel->intelScreen->deviceID))
       ok = i945_miptree_layout(mt);
-      break;
-   case PCI_CHIP_I915_G:
-   case PCI_CHIP_I915_GM:
-   case PCI_CHIP_I830_M:
-   case PCI_CHIP_I855_GM:
-   case PCI_CHIP_I865_G:
-   default:
-      /* All the i830 chips and the i915 use this layout:
-       */
+   else
       ok = i915_miptree_layout(mt);
-      break;
-   }
+#else
+   ok = brw_miptree_layout(mt);
+#endif
 
    if (ok) {
+#ifdef I915
       if (!mt->compressed) {
 	 int align;
 
@@ -125,6 +114,7 @@ intel_miptree_create(struct intel_context *intel,
 
 	 mt->pitch /= cpp;
       }
+#endif /* I915 */
 
       mt->region = intel_region_alloc(intel,
                                       mt->cpp, mt->pitch, mt->total_height);