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| author | Michal Krol <michal@vmware.com> | 2009-09-14 11:22:05 +0200 |
|---|---|---|
| committer | Michal Krol <michal@vmware.com> | 2009-09-14 11:22:05 +0200 |
| commit | 9f273f109875cd9208d4c1c8f5939fb5e507c230 (patch) | |
| tree | 35c8adedcf44cf8eb3bddbb51b5efa766539a07b /src/mesa/drivers/dri/intel/intel_regions.c | |
| parent | fab99092a0879531442d1dd20f971ae7eda824eb (diff) | |
| parent | aad0deee4b2d347bdfc536fe98938ed825bf0f6b (diff) | |
Merge commit 'origin/master' into glsl-pp-rework-2
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_regions.c')
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_regions.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 068a3f3379..a86c66a844 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -196,6 +196,13 @@ intel_region_alloc(struct intel_context *intel, else height = ALIGN(height, 2); + /* If we're untiled, we have to align to 2 rows high because the + * data port accesses 2x2 blocks even if the bottom row isn't to be + * rendered, so failure to align means we could walk off the end of the + * GTT and fault. + */ + height = ALIGN(height, 2); + if (expect_accelerated_upload) { buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region", pitch * cpp * height, 64); |
