diff options
author | Dave Airlie <airlied@redhat.com> | 2009-01-14 10:44:48 +1000 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2009-01-14 10:54:52 +1000 |
commit | 4637235183b80963536f2364e4d50fcb894886dd (patch) | |
tree | bd0b0785aa275b0469498b8a8c3915841b118386 /src/mesa/drivers/dri/r300 | |
parent | 0217ed2cf9b0a538ca03d26b302a7cd57af7dd21 (diff) |
radeon/r200/r300: initial attempt to convert to common context code
Diffstat (limited to 'src/mesa/drivers/dri/r300')
-rw-r--r-- | src/mesa/drivers/dri/r300/Makefile | 3 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r300/r300_cmdbuf.c | 52 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r300/r300_cmdbuf.h | 10 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r300/r300_context.h | 180 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r300/r300_ioctl.c | 8 | ||||
-rw-r--r-- | src/mesa/drivers/dri/r300/radeon_context.h | 118 |
6 files changed, 121 insertions, 250 deletions
diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 3d7122fce2..7357cf74c9 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -77,7 +77,8 @@ COMMON_SYMLINKS = \ radeon_bo_legacy.c \ radeon_cs_legacy.c \ radeon_bo_legacy.h \ - radeon_cs_legacy.h + radeon_cs_legacy.h \ + common_context.h DRI_LIB_DEPS += -ldrm_radeon diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c index 4eac5183b2..bd9d25d2f0 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c @@ -136,10 +136,10 @@ void r300BeginBatch(r300ContextPtr r300, int n, } static void r300PrintStateAtom(r300ContextPtr r300, - struct r300_state_atom *state) + struct radeon_state_atom *state) { int i; - int dwords = (*state->check) (r300, state); + int dwords = (*state->check) (r300->radeon.glCtx, state); fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size); @@ -160,7 +160,7 @@ static void r300PrintStateAtom(r300ContextPtr r300, static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) { BATCH_LOCALS(r300); - struct r300_state_atom *atom; + struct radeon_state_atom *atom; int dwords; cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN); @@ -173,13 +173,13 @@ static INLINE void r300EmitAtoms(r300ContextPtr r300, GLboolean dirty) /* Emit actual atoms */ foreach(atom, &r300->hw.atomlist) { if ((atom->dirty || r300->hw.all_dirty) == dirty) { - dwords = (*atom->check) (r300, atom); + dwords = (*atom->check) (r300->radeon.glCtx, atom); if (dwords) { if (DEBUG_CMDBUF && RADEON_DEBUG & DEBUG_STATE) { r300PrintStateAtom(r300, atom); } if (atom->emit) { - (*atom->emit)(r300, atom); + (*atom->emit)(r300->radeon.glCtx, atom); } else { BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, dwords); @@ -246,15 +246,16 @@ static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt) #define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count) #define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count) -void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom) +void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom) { + r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(r300); drm_r300_cmd_header_t cmd; uint32_t addr, ndw, i; if (!r300->radeon.radeonScreen->kernel_mm) { uint32_t dwords; - dwords = (*atom->check) (r300, atom); + dwords = (*atom->check) (ctx, atom); BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, dwords); END_BATCH(); @@ -284,8 +285,9 @@ void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom) } } -void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom) +void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom) { + r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(r300); drm_r300_cmd_header_t cmd; uint32_t addr, ndw, i, sz; @@ -293,7 +295,7 @@ void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom) if (!r300->radeon.radeonScreen->kernel_mm) { uint32_t dwords; - dwords = (*atom->check) (r300, atom); + dwords = (*atom->check) (ctx, atom); BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_BATCH_TABLE(atom->cmd, dwords); END_BATCH(); @@ -323,8 +325,9 @@ void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom) } } -static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom) +static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom) { + r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(r300); int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd); @@ -353,8 +356,9 @@ static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom) } } -static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom) +static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom) { + r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(r300); struct radeon_renderbuffer *rrb; uint32_t cbpitch; @@ -362,7 +366,7 @@ static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom) rrb = r300->radeon.state.color.rrb; if (r300->radeon.radeonScreen->driScreen->dri2.enabled) { - rrb = fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; + rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; } if (!rrb || !rrb->bo) { fprintf(stderr, "no rrb\n"); @@ -386,8 +390,9 @@ static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom) END_BATCH(); } -static void emit_zb_offset(r300ContextPtr r300, struct r300_state_atom * atom) +static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom) { + r300ContextPtr r300 = R300_CONTEXT(ctx); BATCH_LOCALS(r300); struct radeon_renderbuffer *rrb; uint32_t zbpitch; @@ -411,22 +416,23 @@ static void emit_zb_offset(r300ContextPtr r300, struct r300_state_atom * atom) END_BATCH(); } -static int check_always(r300ContextPtr r300, struct r300_state_atom *atom) +static int check_always(GLcontext *ctx, struct radeon_state_atom *atom) { return atom->cmd_size; } -static int check_variable(r300ContextPtr r300, struct r300_state_atom *atom) +static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom) { + r300ContextPtr r300 = R300_CONTEXT(ctx); int cnt; - if (atom->cmd[0] == CP_PACKET2) { - return 0; - } + if (atom->cmd[0] == CP_PACKET2) { + return 0; + } cnt = packet0_count(r300, atom->cmd); return cnt ? cnt + 1 : 0; } -int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom) +int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom) { int cnt; @@ -434,7 +440,7 @@ int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom) return cnt ? (cnt * 4) + 1 : 0; } -int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom) +int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom) { int cnt; @@ -442,7 +448,7 @@ int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom) return cnt ? (cnt * 6) + 1 : 0; } -int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom) +int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom) { int cnt; @@ -774,7 +780,7 @@ void r300InitCmdBuf(r300ContextPtr r300) if (size > 64 * 256) size = 64 * 256; - size = 64 * 1024 / 4; + size = 64 * 1024 / 4; if (RADEON_DEBUG & (DEBUG_IOCTL | DEBUG_DMA)) { fprintf(stderr, "sizeof(drm_r300_cmd_header_t)=%zd\n", sizeof(drm_r300_cmd_header_t)); @@ -805,7 +811,7 @@ void r300InitCmdBuf(r300ContextPtr r300) */ void r300DestroyCmdBuf(r300ContextPtr r300) { - struct r300_state_atom *atom; + struct radeon_state_atom *atom; radeon_cs_destroy(r300->cmdbuf.cs); foreach(atom, &r300->hw.atomlist) { diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h index bb7e0bf296..f4cc5d3bb1 100644 --- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h +++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h @@ -127,11 +127,11 @@ void r300BeginBatch(r300ContextPtr r300, do { \ } while(0) -void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom); -int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom); +void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom); +int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom); -void emit_r500fp(r300ContextPtr r300, struct r300_state_atom * atom); -int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom); -int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom); +void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom); +int check_r500fp(GLcontext *ctx, struct radeon_state_atom *atom); +int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom); #endif /* __R300_CMDBUF_H__ */ diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 30229ed4fb..e631e81007 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -55,7 +55,7 @@ typedef struct r300_context *r300ContextPtr; #include "radeon_lock.h" #include "main/mm.h" -/* From http://gcc.gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html . +/* From http://gcc. gnu.org/onlinedocs/gcc-3.2.3/gcc/Variadic-Macros.html . I suppose we could inline this and use macro to fetch out __LINE__ and stuff in case we run into trouble with other compilers ... GLUE! */ @@ -194,24 +194,6 @@ struct r300_texture_state { int tc_count; /* number of incoming texture coordinates from VAP */ }; -/** - * A block of hardware state. - * - * When check returns non-zero, the returned number of dwords must be - * copied verbatim into the command buffer in order to update a state atom - * when it is dirty. - */ -struct r300_state_atom { - struct r300_state_atom *next, *prev; - const char *name; /* for debug */ - int cmd_size; /* maximum size in dwords */ - GLuint idx; /* index in an array (e.g. textures) */ - uint32_t *cmd; - GLboolean dirty; - - int (*check) (r300ContextPtr, struct r300_state_atom * atom); - void (*emit) (r300ContextPtr, struct r300_state_atom * atom); -}; #define R300_VPT_CMD_0 0 #define R300_VPT_XSCALE 1 @@ -428,96 +410,96 @@ struct r300_state_atom { * Cache for hardware register state. */ struct r300_hw_state { - struct r300_state_atom atomlist; + struct radeon_state_atom atomlist; GLboolean is_dirty; GLboolean all_dirty; int max_state_size; /* in dwords */ - struct r300_state_atom vpt; /* viewport (1D98) */ - struct r300_state_atom vap_cntl; - struct r300_state_atom vap_index_offset; /* 0x208c r5xx only */ - struct r300_state_atom vof; /* VAP output format register 0x2090 */ - struct r300_state_atom vte; /* (20B0) */ - struct r300_state_atom vap_vf_max_vtx_indx; /* Maximum Vertex Indx Clamp (2134) */ - struct r300_state_atom vap_cntl_status; - struct r300_state_atom vir[2]; /* vap input route (2150/21E0) */ - struct r300_state_atom vic; /* vap input control (2180) */ - struct r300_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */ - struct r300_state_atom vap_clip_cntl; - struct r300_state_atom vap_clip; - struct r300_state_atom vap_pvs_vtx_timeout_reg; /* Vertex timeout register (2288) */ - struct r300_state_atom pvs; /* pvs_cntl (22D0) */ - struct r300_state_atom gb_enable; /* (4008) */ - struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */ - struct r300_state_atom ga_point_s0; /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */ - struct r300_state_atom ga_triangle_stipple; /* (4214) */ - struct r300_state_atom ps; /* pointsize (421C) */ - struct r300_state_atom ga_point_minmax; /* (4230) */ - struct r300_state_atom lcntl; /* line control */ - struct r300_state_atom ga_line_stipple; /* (4260) */ - struct r300_state_atom shade; - struct r300_state_atom polygon_mode; - struct r300_state_atom fogp; /* fog parameters (4294) */ - struct r300_state_atom ga_soft_reset; /* (429C) */ - struct r300_state_atom zbias_cntl; - struct r300_state_atom zbs; /* zbias (42A4) */ - struct r300_state_atom occlusion_cntl; - struct r300_state_atom cul; /* cull cntl (42B8) */ - struct r300_state_atom su_depth_scale; /* (42C0) */ - struct r300_state_atom rc; /* rs control (4300) */ - struct r300_state_atom ri; /* rs interpolators (4310) */ - struct r300_state_atom rr; /* rs route (4330) */ - struct r300_state_atom sc_hyperz; /* (43A4) */ - struct r300_state_atom sc_screendoor; /* (43E8) */ - struct r300_state_atom fp; /* fragment program cntl + nodes (4600) */ - struct r300_state_atom fpt; /* texi - (4620) */ - struct r300_state_atom us_out_fmt; /* (46A4) */ - struct r300_state_atom r500fp; /* r500 fp instructions */ - struct r300_state_atom r500fp_const; /* r500 fp constants */ - struct r300_state_atom fpi[4]; /* fp instructions (46C0/47C0/48C0/49C0) */ - struct r300_state_atom fogs; /* fog state (4BC0) */ - struct r300_state_atom fogc; /* fog color (4BC8) */ - struct r300_state_atom at; /* alpha test (4BD4) */ - struct r300_state_atom fg_depth_src; /* (4BD8) */ - struct r300_state_atom fpp; /* 0x4C00 and following */ - struct r300_state_atom rb3d_cctl; /* (4E00) */ - struct r300_state_atom bld; /* blending (4E04) */ - struct r300_state_atom cmk; /* colormask (4E0C) */ - struct r300_state_atom blend_color; /* constant blend color */ - struct r300_state_atom rop; /* ropcntl */ - struct r300_state_atom cb; /* colorbuffer (4E28) */ - struct r300_state_atom rb3d_dither_ctl; /* (4E50) */ - struct r300_state_atom rb3d_aaresolve_ctl; /* (4E88) */ - struct r300_state_atom rb3d_discard_src_pixel_lte_threshold; /* (4E88) I saw it only written on RV350 hardware.. */ - struct r300_state_atom zs; /* zstencil control (4F00) */ - struct r300_state_atom zstencil_format; - struct r300_state_atom zb; /* z buffer (4F20) */ - struct r300_state_atom zb_depthclearvalue; /* (4F28) */ - struct r300_state_atom unk4F30; /* (4F30) */ - struct r300_state_atom zb_hiz_offset; /* (4F44) */ - struct r300_state_atom zb_hiz_pitch; /* (4F54) */ - - struct r300_state_atom vpi; /* vp instructions */ - struct r300_state_atom vpp; /* vp parameters */ - struct r300_state_atom vps; /* vertex point size (?) */ - struct r300_state_atom vpucp[6]; /* vp user clip plane - 6 */ + struct radeon_state_atom vpt; /* viewport (1D98) */ + struct radeon_state_atom vap_cntl; + struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */ + struct radeon_state_atom vof; /* VAP output format register 0x2090 */ + struct radeon_state_atom vte; /* (20B0) */ + struct radeon_state_atom vap_vf_max_vtx_indx; /* Maximum Vertex Indx Clamp (2134) */ + struct radeon_state_atom vap_cntl_status; + struct radeon_state_atom vir[2]; /* vap input route (2150/21E0) */ + struct radeon_state_atom vic; /* vap input control (2180) */ + struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */ + struct radeon_state_atom vap_clip_cntl; + struct radeon_state_atom vap_clip; + struct radeon_state_atom vap_pvs_vtx_timeout_reg; /* Vertex timeout register (2288) */ + struct radeon_state_atom pvs; /* pvs_cntl (22D0) */ + struct radeon_state_atom gb_enable; /* (4008) */ + struct radeon_state_atom gb_misc; /* Multisampling position shifts ? (4010) */ + struct radeon_state_atom ga_point_s0; /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */ + struct radeon_state_atom ga_triangle_stipple; /* (4214) */ + struct radeon_state_atom ps; /* pointsize (421C) */ + struct radeon_state_atom ga_point_minmax; /* (4230) */ + struct radeon_state_atom lcntl; /* line control */ + struct radeon_state_atom ga_line_stipple; /* (4260) */ + struct radeon_state_atom shade; + struct radeon_state_atom polygon_mode; + struct radeon_state_atom fogp; /* fog parameters (4294) */ + struct radeon_state_atom ga_soft_reset; /* (429C) */ + struct radeon_state_atom zbias_cntl; + struct radeon_state_atom zbs; /* zbias (42A4) */ + struct radeon_state_atom occlusion_cntl; + struct radeon_state_atom cul; /* cull cntl (42B8) */ + struct radeon_state_atom su_depth_scale; /* (42C0) */ + struct radeon_state_atom rc; /* rs control (4300) */ + struct radeon_state_atom ri; /* rs interpolators (4310) */ + struct radeon_state_atom rr; /* rs route (4330) */ + struct radeon_state_atom sc_hyperz; /* (43A4) */ + struct radeon_state_atom sc_screendoor; /* (43E8) */ + struct radeon_state_atom fp; /* fragment program cntl + nodes (4600) */ + struct radeon_state_atom fpt; /* texi - (4620) */ + struct radeon_state_atom us_out_fmt; /* (46A4) */ + struct radeon_state_atom r500fp; /* r500 fp instructions */ + struct radeon_state_atom r500fp_const; /* r500 fp constants */ + struct radeon_state_atom fpi[4]; /* fp instructions (46C0/47C0/48C0/49C0) */ + struct radeon_state_atom fogs; /* fog state (4BC0) */ + struct radeon_state_atom fogc; /* fog color (4BC8) */ + struct radeon_state_atom at; /* alpha test (4BD4) */ + struct radeon_state_atom fg_depth_src; /* (4BD8) */ + struct radeon_state_atom fpp; /* 0x4C00 and following */ + struct radeon_state_atom rb3d_cctl; /* (4E00) */ + struct radeon_state_atom bld; /* blending (4E04) */ + struct radeon_state_atom cmk; /* colormask (4E0C) */ + struct radeon_state_atom blend_color; /* constant blend color */ + struct radeon_state_atom rop; /* ropcntl */ + struct radeon_state_atom cb; /* colorbuffer (4E28) */ + struct radeon_state_atom rb3d_dither_ctl; /* (4E50) */ + struct radeon_state_atom rb3d_aaresolve_ctl; /* (4E88) */ + struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold; /* (4E88) I saw it only written on RV350 hardware.. */ + struct radeon_state_atom zs; /* zstencil control (4F00) */ + struct radeon_state_atom zstencil_format; + struct radeon_state_atom zb; /* z buffer (4F20) */ + struct radeon_state_atom zb_depthclearvalue; /* (4F28) */ + struct radeon_state_atom unk4F30; /* (4F30) */ + struct radeon_state_atom zb_hiz_offset; /* (4F44) */ + struct radeon_state_atom zb_hiz_pitch; /* (4F54) */ + + struct radeon_state_atom vpi; /* vp instructions */ + struct radeon_state_atom vpp; /* vp parameters */ + struct radeon_state_atom vps; /* vertex point size (?) */ + struct radeon_state_atom vpucp[6]; /* vp user clip plane - 6 */ /* 8 texture units */ /* the state is grouped by function and not by texture unit. This makes single unit updates really awkward - we are much better off updating the whole thing at once */ struct { - struct r300_state_atom filter; - struct r300_state_atom filter_1; - struct r300_state_atom size; - struct r300_state_atom format; - struct r300_state_atom pitch; - struct r300_state_atom offset; - struct r300_state_atom chroma_key; - struct r300_state_atom border_color; + struct radeon_state_atom filter; + struct radeon_state_atom filter_1; + struct radeon_state_atom size; + struct radeon_state_atom format; + struct radeon_state_atom pitch; + struct radeon_state_atom offset; + struct radeon_state_atom chroma_key; + struct radeon_state_atom border_color; } tex; - struct r300_state_atom txe; /* tex enable (4104) */ + struct radeon_state_atom txe; /* tex enable (4104) */ r300TexObj *textures[R300_MAX_TEXTURE_UNITS]; }; @@ -841,10 +823,6 @@ struct r300_swtcl_info { /* Fallback rasterization functions */ - // r200_point_func draw_point; - // r200_line_func draw_line; - // r200_tri_func draw_tri; - GLuint hw_primitive; GLenum render_primitive; GLuint numverts; diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c index 6d7b191b24..064732d458 100644 --- a/src/mesa/drivers/dri/r300/r300_ioctl.c +++ b/src/mesa/drivers/dri/r300/r300_ioctl.c @@ -387,7 +387,7 @@ static void r300EmitClearState(GLcontext * ctx) FP_SELA(0, NO, W, FP_TMP(0), 0, 0)); END_BATCH(); } else { - struct r300_state_atom r500fp; + struct radeon_state_atom r500fp; uint32_t _cmd[10]; R300_STATECHANGE(r300, fp); @@ -443,7 +443,7 @@ static void r300EmitClearState(GLcontext * ctx) R500_ALU_RGBA_A_SWIZ_0; r500fp.cmd[7] = 0; - emit_r500fp(r300, &r500fp); + emit_r500fp(ctx, &r500fp); } BEGIN_BATCH(2); @@ -484,7 +484,7 @@ static void r300EmitClearState(GLcontext * ctx) END_BATCH(); if (has_tcl) { - struct r300_state_atom vpu; + struct radeon_state_atom vpu; uint32_t _cmd[10]; R300_STATECHANGE(r300, pvs); R300_STATECHANGE(r300, vpi); @@ -528,7 +528,7 @@ static void r300EmitClearState(GLcontext * ctx) PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE); vpu.cmd[8] = 0x0; - emit_vpu(r300, &vpu); + emit_vpu(ctx, &vpu); } } diff --git a/src/mesa/drivers/dri/r300/radeon_context.h b/src/mesa/drivers/dri/r300/radeon_context.h index d5bbf2928d..7dfc3b3b91 100644 --- a/src/mesa/drivers/dri/r300/radeon_context.h +++ b/src/mesa/drivers/dri/r300/radeon_context.h @@ -49,20 +49,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drm.h" #include "dri_util.h" -struct radeon_context; -typedef struct radeon_context radeonContextRec; -typedef struct radeon_context *radeonContextPtr; - -/* Rasterizing fallbacks */ -/* See correponding strings in r200_swtcl.c */ -#define RADEON_FALLBACK_TEXTURE 0x0001 -#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 -#define RADEON_FALLBACK_STENCIL 0x0004 -#define RADEON_FALLBACK_RENDER_MODE 0x0008 -#define RADEON_FALLBACK_BLEND_EQ 0x0010 -#define RADEON_FALLBACK_BLEND_FUNC 0x0020 -#define RADEON_FALLBACK_DISABLE 0x0040 -#define RADEON_FALLBACK_BORDER_MODE 0x0080 +#include "radeon_screen.h" +#include "common_context.h" #if R200_MERGED extern void radeonFallback(GLcontext * ctx, GLuint bit, GLboolean mode); @@ -99,96 +87,6 @@ extern void radeonTclFallback(GLcontext * ctx, GLuint bit, GLboolean mode); #define TCL_FALLBACK( ctx, bit, mode ) ; #endif -struct radeon_dri_mirror { - __DRIcontextPrivate *context; /* DRI context */ - __DRIscreenPrivate *screen; /* DRI screen */ - /** - * DRI drawable bound to this context for drawing. - */ - __DRIdrawablePrivate *drawable; - - /** - * DRI drawable bound to this context for reading. - */ - __DRIdrawablePrivate *readable; - - drm_context_t hwContext; - drm_hw_lock_t *hwLock; - int fd; - int drmMinor; -}; - -/** - * Derived state for internal purposes. - */ -struct radeon_scissor_state { - drm_clip_rect_t rect; - GLboolean enabled; - - GLuint numClipRects; /* Cliprects active */ - GLuint numAllocedClipRects; /* Cliprects available */ - drm_clip_rect_t *pClipRects; -}; - -struct radeon_colorbuffer_state { - GLuint clear; - struct radeon_renderbuffer *rrb; -}; - -struct radeon_state { - struct radeon_colorbuffer_state color; - struct radeon_scissor_state scissor; - struct radeon_renderbuffer *depth_buffer; -}; - -/** - * Common per-context variables shared by R200 and R300. - * R200- and R300-specific code "derive" their own context from this - * structure. - */ -struct radeon_context { - GLcontext *glCtx; /* Mesa context */ - radeonScreenPtr radeonScreen; /* Screen private DRI data */ - - /* Fallback state */ - GLuint Fallback; - GLuint TclFallback; - - /* Page flipping */ - GLuint doPageFlip; - - /* Drawable, cliprect and scissor information */ - GLuint numClipRects; /* Cliprects for the draw buffer */ - drm_clip_rect_t *pClipRects; - unsigned int lastStamp; - GLboolean lost_context; - drm_radeon_sarea_t *sarea; /* Private SAREA data */ - - /* Mirrors of some DRI state */ - struct radeon_dri_mirror dri; - - /* Busy waiting */ - GLuint do_usleeps; - GLuint do_irqs; - GLuint irqsEmitted; - drm_radeon_irq_wait_t iw; - - /* buffer swap */ - int64_t swap_ust; - int64_t swap_missed_ust; - - GLuint swap_count; - GLuint swap_missed_count; - - /* Derived state */ - struct radeon_state state; - - /* Configuration cache - */ - driOptionCache optionCache; -}; - -#define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) extern void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, @@ -216,18 +114,6 @@ extern int RADEON_DEBUG; #define RADEON_DEBUG 0 #endif -#define DEBUG_TEXTURE 0x0001 -#define DEBUG_STATE 0x0002 -#define DEBUG_IOCTL 0x0004 -#define DEBUG_PRIMS 0x0008 -#define DEBUG_VERTS 0x0010 -#define DEBUG_FALLBACKS 0x0020 -#define DEBUG_VFMT 0x0040 -#define DEBUG_CODEGEN 0x0080 -#define DEBUG_VERBOSE 0x0100 -#define DEBUG_DRI 0x0200 -#define DEBUG_DMA 0x0400 -#define DEBUG_SANITY 0x0800 #define DEBUG_SYNC 0x1000 #define DEBUG_PIXEL 0x2000 #define DEBUG_MEMORY 0x4000 |