diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2010-02-04 10:45:13 -0500 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2010-02-04 10:46:36 -0500 |
| commit | 339d42b4e684343c743ea819337c057c0046323f (patch) | |
| tree | 0b73bf856cefe07ea569da84f5cd4ce60ca2f9d6 /src/mesa/drivers/dri/r600/r600_blit.c | |
| parent | f769ab0fa63754de317bafe2a7baf8fe401b961c (diff) | |
r600: reduce number of cache flushes
We don't need to flush so often. Next step
would be to move the flushing to the drm and only
flush after each command buffer rather than each
draw.
Diffstat (limited to 'src/mesa/drivers/dri/r600/r600_blit.c')
| -rw-r--r-- | src/mesa/drivers/dri/r600/r600_blit.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c index d7cd59ade6..4bb77a398f 100644 --- a/src/mesa/drivers/dri/r600/r600_blit.c +++ b/src/mesa/drivers/dri/r600/r600_blit.c @@ -1652,6 +1652,7 @@ unsigned r600_blit(GLcontext *ctx, CB_ACTION_ENA_bit | (1 << (id + 6))); /* 5 */ + /* XXX drm should handle this in fence submit */ r700WaitForIdleClean(context); radeonFlush(ctx); |