diff options
| author | Christoph Bumiller <e0425955@student.tuwien.ac.at> | 2010-09-02 18:31:49 +0200 |
|---|---|---|
| committer | Christoph Bumiller <e0425955@student.tuwien.ac.at> | 2010-09-02 18:31:49 +0200 |
| commit | 222d2f2ac2c7d93cbc0643082c78278ad2c8cfce (patch) | |
| tree | b79152c238022b2a901201c22e5809ac520732bf /src/mesa/drivers/dri/r600/r700_state.c | |
| parent | 443abc80db9e1a288ce770e76cccd43664348098 (diff) | |
| parent | e73c5501b2fe20290d1b691c85a5d82ac3a0431c (diff) | |
Merge remote branch 'origin/master' into nv50-compiler
Conflicts:
src/gallium/drivers/nv50/nv50_program.c
Diffstat (limited to 'src/mesa/drivers/dri/r600/r700_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/r600/r700_state.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 5ea8918611..925b4ffe6d 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1580,7 +1580,16 @@ static void r700InitSQConfig(GLcontext * ctx) CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit); else SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit); - SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit); + + if(GL_TRUE == r700->bShaderUseMemConstant) + { + CLEARbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit); + } + else + { + SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit); + } + SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit); SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask); SETfield(r700->sq_config.SQ_CONFIG.u32All, vs_prio, VS_PRIO_shift, VS_PRIO_mask); @@ -1689,8 +1698,9 @@ void r700InitState(GLcontext * ctx) //------------------- SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit); } - /* Do scale XY and Z by 1/W0. */ - r700->bEnablePerspective = GL_TRUE; + /* Do scale XY and Z by 1/W0. */ + r700->bEnablePerspective = GL_TRUE; + CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit); CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit); SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit); |