diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2009-09-14 18:05:15 -0400 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2009-09-14 18:10:24 -0400 |
| commit | 364ca57aff733e8ee5f417b3f8719514f443315f (patch) | |
| tree | 95b08d99b72f1afe388dbf239ce9fb03ec087664 /src/mesa/drivers/dri/r600 | |
| parent | f662cedae446b124ff3f370c21cc7bb2e08244a0 (diff) | |
r600: add span support for 1D tiles
1D tile span support for depth/stencil/color/textures
Z and stencil buffers are always tiled, so this fixes
sw access to Z and stencil buffers. color and textures
are currently linear, but this adds span support when we
implement 1D tiling.
This fixes the text in progs/demos/engine and progs/tests/z*
Diffstat (limited to 'src/mesa/drivers/dri/r600')
| -rw-r--r-- | src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/r600/r700_chip.c | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h b/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h index 9d5aa3c7e4..edd85b0fac 100644 --- a/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h +++ b/src/mesa/drivers/dri/r600/r600_reg_auto_r6xx.h @@ -1366,6 +1366,7 @@ enum { DB_DEPTH_INFO__READ_SIZE_bit = 1 << 3, DB_DEPTH_INFO__ARRAY_MODE_mask = 0x0f << 15, DB_DEPTH_INFO__ARRAY_MODE_shift = 15, + ARRAY_1D_TILED_THIN1 = 0x02, ARRAY_2D_TILED_THIN1 = 0x04, TILE_SURFACE_ENABLE_bit = 1 << 25, TILE_COMPACT_bit = 1 << 26, @@ -1449,6 +1450,7 @@ enum { CB_COLOR0_INFO__ARRAY_MODE_shift = 8, ARRAY_LINEAR_GENERAL = 0x00, ARRAY_LINEAR_ALIGNED = 0x01, +/* ARRAY_1D_TILED_THIN1 = 0x02, */ /* ARRAY_2D_TILED_THIN1 = 0x04, */ NUMBER_TYPE_mask = 0x07 << 12, NUMBER_TYPE_shift = 12, diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 1b56059197..06d7e9c9ab 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -351,7 +351,7 @@ static void r700SetDepthTarget(context_t *context) SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16, DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask); } - SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1, + SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_1D_TILED_THIN1, DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask); /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */ } |