radeon/r200/r300: Fix swtcl flushing not to invalidate dma region.

We were check command buffer sizes too alte so allocated dma regions
were freed before relocations so space checking failed.

3 files changed, 22 insertions, 17 deletions

diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index cb47484de1..5c4b4abaca 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -342,6 +342,7 @@ struct radeon_swtcl_info {
 	struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 	GLuint vertex_attr_count;
 
+	GLuint primitive_counter;
 };
 
 #define RADEON_MAX_AOS_ARRAYS		16
diff --git a/src/mesa/drivers/dri/radeon/radeon_dma.c b/src/mesa/drivers/dri/radeon/radeon_dma.c
index 51f764cf47..7aa59675b7 100644
--- a/src/mesa/drivers/dri/radeon/radeon_dma.c
+++ b/src/mesa/drivers/dri/radeon/radeon_dma.c
@@ -428,7 +428,6 @@ rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize )
 {
 	GLuint bytes = vsize * nverts;
 	void *head;
-restart:
 	if (RADEON_DEBUG & DEBUG_IOCTL)
 		fprintf(stderr, "%s\n", __FUNCTION__);
 	if (is_empty_list(&rmesa->dma.reserved)
@@ -437,13 +436,7 @@ restart:
 	}
 
         if (!rmesa->dma.flush) {
-		/* make sure we have enough space to use this in cmdbuf */
-   		rcommonEnsureCmdBufSpace(rmesa,
-			      radeonCountStateEmitSize( rmesa ) + (20*sizeof(int)),
-			      __FUNCTION__);
 		/* if cmdbuf flushed DMA restart */
-		if (is_empty_list(&rmesa->dma.reserved))
-			goto restart;
                 rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
                 rmesa->dma.flush = rcommon_flush_last_swtcl_prim;
         }
diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
index 14d5b5a2af..c9e399f9b6 100644
--- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
@@ -223,13 +223,23 @@ static void radeonSetVertexFormat( GLcontext *ctx )
 
 static void radeonRenderStart( GLcontext *ctx )
 {
-   r100ContextPtr rmesa = R100_CONTEXT( ctx );
-
-   radeonSetVertexFormat( ctx );
-   
-   if (rmesa->radeon.dma.flush != 0 && 
-       rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
-      rmesa->radeon.dma.flush( ctx );
+    r100ContextPtr rmesa = R100_CONTEXT( ctx );
+
+    radeonSetVertexFormat( ctx );
+
+    if (rmesa->radeon.dma.flush != 0 &&
+            rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
+        rmesa->radeon.dma.flush( ctx );
+
+    if (!rmesa->radeon.swtcl.primitive_counter) {
+        if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
+                    radeonCountStateEmitSize( &rmesa->radeon ) +
+                    (8 + 8 + 7), /* scissor + primis + VertexAOS */
+                    __FUNCTION__))
+            rmesa->radeon.swtcl.primitive_counter = 0;
+        else
+            rmesa->radeon.swtcl.primitive_counter = 1;
+    }
 }
 
 
@@ -284,9 +294,6 @@ void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
 {
    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 
-   rcommonEnsureCmdBufSpace(&rmesa->radeon,
-			    radeonCountStateEmitSize( &rmesa->radeon ) + (12*sizeof(int)),
-			    __FUNCTION__);
 
 
    radeonEmitState(&rmesa->radeon);
@@ -301,6 +308,9 @@ void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
 		       rmesa->radeon.swtcl.hw_primitive,
 		       rmesa->radeon.swtcl.numverts);
 
+
+   rmesa->radeon.swtcl.primitive_counter = 0;
+
 }
 
 /*
@@ -804,6 +814,7 @@ void radeonInitSwtcl( GLcontext *ctx )
    if (firsttime) {
       init_rast_tab();
       firsttime = 0;
+      rmesa->radeon.swtcl.primitive_counter = 0;
    }
 
    tnl->Driver.Render.Start = radeonRenderStart;