diff options
| author | Eric Anholt <eric@anholt.net> | 2010-10-06 11:19:48 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-10-06 12:13:08 -0700 |
| commit | 1fdc8c007ea66b4c9866bf2c679653a005307fa5 (patch) | |
| tree | 8b3682c246560cf7666f37510ae3a968085b63a0 /src/mesa/drivers | |
| parent | a760b5b509f85991a10400977576afabcedbb3c5 (diff) | |
i965: Add support for gl_FrontFacing on gen6.
Fixes glsl1-gl_FrontFacing var (2) with new FS.
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.cpp | 49 |
1 files changed, 39 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index c5013f0574..1ccf695a59 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -830,16 +830,33 @@ fs_reg * fs_visitor::emit_frontfacing_interpolation(ir_variable *ir) { fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); - struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); - /* bit 31 is "primitive is back face", so checking < (1 << 31) gives - * us front face - */ - fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, - *reg, - fs_reg(r1_6ud), - fs_reg(1u << 31))); - inst->conditional_mod = BRW_CONDITIONAL_L; - emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u))); + + /* The frontfacing comes in as a bit in the thread payload. */ + if (intel->gen >= 6) { + emit(fs_inst(BRW_OPCODE_ASR, + *reg, + fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)), + fs_reg(15))); + emit(fs_inst(BRW_OPCODE_NOT, + *reg, + *reg)); + emit(fs_inst(BRW_OPCODE_AND, + *reg, + *reg, + fs_reg(1))); + } else { + fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); + struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); + /* bit 31 is "primitive is back face", so checking < (1 << 31) gives + * us front face + */ + fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, + *reg, + fs_reg(r1_6ud), + fs_reg(1u << 31))); + inst->conditional_mod = BRW_CONDITIONAL_L; + emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u))); + } return reg; } @@ -2818,6 +2835,18 @@ fs_visitor::generate_code() case BRW_OPCODE_XOR: brw_XOR(p, dst, src[0], src[1]); break; + case BRW_OPCODE_NOT: + brw_NOT(p, dst, src[0]); + break; + case BRW_OPCODE_ASR: + brw_ASR(p, dst, src[0], src[1]); + break; + case BRW_OPCODE_SHR: + brw_SHR(p, dst, src[0], src[1]); + break; + case BRW_OPCODE_SHL: + brw_SHL(p, dst, src[0], src[1]); + break; case BRW_OPCODE_CMP: brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); |