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authorKenneth Graunke <kenneth@whitecape.org>2011-02-24 17:49:07 -0800
committerKenneth Graunke <kenneth@whitecape.org>2011-02-25 15:30:45 -0800
commit58f7c9c72ee52527610b26ca8a137dd88c082c89 (patch)
treec1f48f12789b77d1c108682df9e7cfd2d441c657 /src/mesa/drivers
parent2830b1ae9032666e62460de5aece8db843c51c14 (diff)
i965/fs: Initial plumbing to support TXD.
This adds the opcode and the code to convert ir_txd to OPCODE_TXD; it doesn't actually add support yet.
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp12
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.h2
2 files changed, 14 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 552641b623..9bdcda780e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -213,6 +213,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
return 2;
case FS_OPCODE_TEX:
case FS_OPCODE_TXB:
+ case FS_OPCODE_TXD:
case FS_OPCODE_TXL:
return 1;
case FS_OPCODE_FB_WRITE:
@@ -1200,6 +1201,8 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate)
}
/* gen4's SIMD8 sampler always has the slots for u,v,r present. */
mlen += 3;
+ } else if (ir->op == ir_txd) {
+ assert(!"TXD isn't supported on gen4 yet.");
} else {
/* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
* instructions. We'll need to do SIMD16 here.
@@ -1253,6 +1256,8 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate)
inst = emit(fs_inst(FS_OPCODE_TXL, dst));
break;
case ir_txd:
+ inst = emit(fs_inst(FS_OPCODE_TXD, dst));
+ break;
case ir_txf:
assert(!"GLSL 1.30 features unsupported");
break;
@@ -2315,6 +2320,9 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_LOD_GEN5;
}
break;
+ case FS_OPCODE_TXD:
+ assert(!"TXD isn't supported on gen5+ yet.");
+ break;
}
} else {
switch (inst->opcode) {
@@ -2349,6 +2357,9 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
}
break;
+ case FS_OPCODE_TXD:
+ assert(!"TXD isn't supported on gen4 yet.");
+ break;
}
}
assert(msg_type != -1);
@@ -3624,6 +3635,7 @@ fs_visitor::generate_code()
break;
case FS_OPCODE_TEX:
case FS_OPCODE_TXB:
+ case FS_OPCODE_TXD:
case FS_OPCODE_TXL:
generate_tex(inst, dst, src[0]);
break;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 8352760acf..dc030ae5b5 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -71,6 +71,7 @@ enum fs_opcodes {
FS_OPCODE_LINTERP,
FS_OPCODE_TEX,
FS_OPCODE_TXB,
+ FS_OPCODE_TXD,
FS_OPCODE_TXL,
FS_OPCODE_DISCARD_NOT,
FS_OPCODE_DISCARD_AND,
@@ -309,6 +310,7 @@ public:
{
return (opcode == FS_OPCODE_TEX ||
opcode == FS_OPCODE_TXB ||
+ opcode == FS_OPCODE_TXD ||
opcode == FS_OPCODE_TXL);
}