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authorEric Anholt <eric@anholt.net>2011-02-21 16:24:41 -0800
committerEric Anholt <eric@anholt.net>2011-02-21 16:36:09 -0800
commit9e872a5865c66ed0a518dd1c6c54e72f3afa71f1 (patch)
treead2acdda3b9afaea96addea999beb8aa58671902 /src/mesa/drivers
parent12f25eb6d5521ad2dc61eab08331c1ea8d3c67f7 (diff)
i965: Fix VB packet reuse when offset for the new buffer isn't stride aligned.
Fixes regression in scissor-stencil-clear and 5 other tests.
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw_upload.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 17af046b50..b15c05a7ad 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -470,7 +470,7 @@ static void brw_prepare_vertices(struct brw_context *brw)
d = brw->vb.buffers[i].offset - brw->vb.current_buffers[i].offset;
if (delta == 0)
delta = d / brw->vb.current_buffers[i].stride;
- else if (delta * brw->vb.current_buffers[i].stride != d)
+ if (delta * brw->vb.current_buffers[i].stride != d)
break;
}