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| author | Brian <brian.paul@tungstengraphics.com> | 2008-02-05 14:23:34 -0700 |
|---|---|---|
| committer | Ben Skeggs <skeggsb@gmail.com> | 2008-02-15 13:50:31 +1100 |
| commit | df2ab198eb49333f01c8f10bea2033bea732d755 (patch) | |
| tree | 588cc90404d99f6ad27a58e1d8410b1c3ab73ceb /src/mesa/pipe/cell/spu/spu_main.c | |
| parent | 2ec5ae5e504d8bf82cdecae8569dc12b8d62c055 (diff) | |
Cell: re-enable inlined vertex buffers
Vertex data must be on a 16-byte address/offset so SIMD operations will work
properly in the SPU code.
Diffstat (limited to 'src/mesa/pipe/cell/spu/spu_main.c')
| -rw-r--r-- | src/mesa/pipe/cell/spu/spu_main.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/pipe/cell/spu/spu_main.c b/src/mesa/pipe/cell/spu/spu_main.c index 4f126d5e5b..e375197fe6 100644 --- a/src/mesa/pipe/cell/spu/spu_main.c +++ b/src/mesa/pipe/cell/spu/spu_main.c @@ -387,7 +387,7 @@ cmd_batch(uint opcode) = (struct cell_command_render *) &buffer[pos]; uint pos_incr; cmd_render(render, &pos_incr); - pos += sizeof(*render) / 8 + ((pos_incr + 1) / 2); + pos += pos_incr; } break; case CELL_CMD_RELEASE_VERTS: @@ -541,6 +541,7 @@ main(main_param_t speid, main_param_t argp) (void) speid; ASSERT(sizeof(tile_t) == TILE_SIZE * TILE_SIZE * 4); + ASSERT(sizeof(struct cell_command_render) % 8 == 0); one_time_init(); |