nouveau: avoid relocations where possible.

Potential relocations are emitted as NOPs where they're needed.  In the
event a buffer moves, the pushbuf code will emit the relevant state
changes into the NOPs.

Just a start, more work is needed to get this looking how I want it to.

1 files changed, 25 insertions, 7 deletions

diff --git a/src/mesa/pipe/nv40/nv40_state.c b/src/mesa/pipe/nv40/nv40_state.c
index c619948b55..bb435b106b 100644
--- a/src/mesa/pipe/nv40/nv40_state.c
+++ b/src/mesa/pipe/nv40/nv40_state.c
@@ -603,33 +603,51 @@ nv40_set_framebuffer_state(struct pipe_context *pipe,
 	}
 
 	if (rt_enable & NV40TCL_RT_ENABLE_COLOR0) {
-		BEGIN_RING(curie, NV40TCL_COLOR0_PITCH, 1);
-		OUT_RING  (rt[0]->pitch * rt[0]->cpp);
 		nv40->rt[0] = rt[0]->buffer;
+		BEGIN_RING(curie, NV40TCL_DMA_COLOR0, 1);
+		OUT_RELOCo(nv40->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+		BEGIN_RING(curie, NV40TCL_COLOR0_PITCH, 2);
+		OUT_RING  (rt[0]->pitch * rt[0]->cpp);
+		OUT_RELOCl(nv40->rt[0], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 	}
 
 	if (rt_enable & NV40TCL_RT_ENABLE_COLOR1) {
-		BEGIN_RING(curie, NV40TCL_COLOR1_PITCH, 2);
-		OUT_RING  (rt[1]->pitch * rt[1]->cpp);
 		nv40->rt[1] = rt[1]->buffer;
+		BEGIN_RING(curie, NV40TCL_DMA_COLOR1, 1);
+		OUT_RELOCo(nv40->rt[1], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+		BEGIN_RING(curie, NV40TCL_COLOR1_OFFSET, 2);
+		OUT_RELOCl(nv40->rt[1], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+		OUT_RING  (rt[1]->pitch * rt[1]->cpp);
 	}
 
 	if (rt_enable & NV40TCL_RT_ENABLE_COLOR2) {
+		nv40->rt[2] = rt[2]->buffer;
+		BEGIN_RING(curie, NV40TCL_DMA_COLOR2, 1);
+		OUT_RELOCo(nv40->rt[2], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+		BEGIN_RING(curie, NV40TCL_COLOR2_OFFSET, 1);
+		OUT_RELOCl(nv40->rt[2], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 		BEGIN_RING(curie, NV40TCL_COLOR2_PITCH, 1);
 		OUT_RING  (rt[2]->pitch * rt[2]->cpp);
-		nv40->rt[2] = rt[2]->buffer;
 	}
 
 	if (rt_enable & NV40TCL_RT_ENABLE_COLOR3) {
+		nv40->rt[3] = rt[3]->buffer;
+		BEGIN_RING(curie, NV40TCL_DMA_COLOR3, 1);
+		OUT_RELOCo(nv40->rt[3], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+		BEGIN_RING(curie, NV40TCL_COLOR3_OFFSET, 1);
+		OUT_RELOCl(nv40->rt[3], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 		BEGIN_RING(curie, NV40TCL_COLOR3_PITCH, 1);
 		OUT_RING  (rt[3]->pitch * rt[3]->cpp);
-		nv40->rt[3] = rt[3]->buffer;
 	}
 
 	if (zeta_format) {
+		nv40->zeta = zeta->buffer;
+		BEGIN_RING(curie, NV40TCL_DMA_ZETA, 1);
+		OUT_RELOCo(nv40->zeta, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+		BEGIN_RING(curie, NV40TCL_ZETA_OFFSET, 1);
+		OUT_RELOCl(nv40->zeta, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 		BEGIN_RING(curie, NV40TCL_ZETA_PITCH, 1);
 		OUT_RING  (zeta->pitch * zeta->cpp);
-		nv40->zeta = zeta->buffer;
 	}
 
 	nv40->rt_enable = rt_enable;