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authorBrian Paul <brianp@vmware.com>2010-06-02 17:37:42 -0600
committerBrian Paul <brianp@vmware.com>2010-06-02 17:43:39 -0600
commitdfe9dec04f707d61633665785600156d282d0d39 (patch)
treef8df2f4a357d8de90e483e0e63ccd6ba3bf2a0d4 /src/mesa/state_tracker
parent14b7fdb8ac1d83bad1d8612b95a8fdd7ca68ff1e (diff)
st/mesa: fix indirect addressing of input/output regs
This fixes an issue that was missed with commit 9f544394c1d059ce09c8bb2b5e11f5e871c7915f. Fixes piglit glsl-texcoord-array.shader_test
Diffstat (limited to 'src/mesa/state_tracker')
-rw-r--r--src/mesa/state_tracker/st_mesa_to_tgsi.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c b/src/mesa/state_tracker/st_mesa_to_tgsi.c
index 6df6cdfe03..35016d80e6 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -319,10 +319,15 @@ translate_src( struct st_translate *t,
if (SrcReg->RelAddr) {
src = ureg_src_indirect( src, ureg_src(t->address[0]));
- /* If SrcReg->Index was negative, it was set to zero in
- * src_register(). Reassign it now.
- */
- src.Index = SrcReg->Index;
+ if (SrcReg->File != PROGRAM_INPUT &&
+ SrcReg->File != PROGRAM_OUTPUT) {
+ /* If SrcReg->Index was negative, it was set to zero in
+ * src_register(). Reassign it now. But don't do this
+ * for input/output regs since they get remapped while
+ * const buffers don't.
+ */
+ src.Index = SrcReg->Index;
+ }
}
return src;