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authorEric Anholt <eric@anholt.net>2009-08-07 18:09:31 -0700
committerEric Anholt <eric@anholt.net>2009-09-04 14:12:36 -0700
commit945d34e88ab7413299227fea56acc746010bb2e9 (patch)
tree919a410d9938f56ef2ddf223145b9941b04a0c18 /src/mesa
parent94d3b832cc5c73544c478804531e16644483d8be (diff)
intel: Align untiled region height to 2 according to 965 docs.
This may or may not be required pre-965, but it doesn't seem unlikely, and I'd rather be safe. (cherry picked from commit b053474378633249be0e9f24010650ffb816229a)
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/intel/intel_regions.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 0aa5b8c02c..b8d2dec4cb 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -114,6 +114,13 @@ intel_region_alloc(struct intel_context *intel,
{
dri_bo *buffer;
+ /* If we're untiled, we have to align to 2 rows high because the
+ * data port accesses 2x2 blocks even if the bottom row isn't to be
+ * rendered, so failure to align means we could walk off the end of the
+ * GTT and fault.
+ */
+ height = ALIGN(height, 2);
+
if (expect_accelerated_upload) {
buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
pitch * cpp * height, 64);