This patch adds the missing NV_vertex_program2 and NV_vertex_program3

instructions to the various internal tables.  It does not add support for
them to the parser nor does it add support for them to the program
interpreter.

It also corrects some errors in the comments in program_instruction.h.

This patch breaks the instruction union in t_vb_arbprogram.h.  The opcode
field in that union was only 6 bits.  When there were only 59+3 instructions
that worked fine. However, this patch increases the base instruction count
to 69.  This requires 7 bits.  The problem is that increasing the opcode
width to 7 bits increases the size of instruction::rsw to 33 bits.  I've
increased the size of the union to 64-bit, but this is just a temporary hack
(and probably breaks the build on some systems).

4 files changed, 58 insertions, 45 deletions

diff --git a/src/mesa/shader/program.c b/src/mesa/shader/program.c
index a77c447e28..d46fadefca 100644
--- a/src/mesa/shader/program.c
+++ b/src/mesa/shader/program.c
@@ -978,7 +978,12 @@ struct instruction_info
 static const struct instruction_info InstInfo[MAX_OPCODE] = {
    { OPCODE_ABS,    "ABS",   1 },
    { OPCODE_ADD,    "ADD",   2 },
+   { OPCODE_ARA,    "ARA",   1 },
    { OPCODE_ARL,    "ARL",   1 },
+   { OPCODE_ARL_NV, "ARL",   1 },
+   { OPCODE_ARR,    "ARL",   1 },
+   { OPCODE_BRA,    "BRA",   1 },
+   { OPCODE_CAL,    "CAL",   1 },
    { OPCODE_CMP,    "CMP",   3 },
    { OPCODE_COS,    "COS",   1 },
    { OPCODE_DDX,    "DDX",   1 },
@@ -1008,9 +1013,12 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = {
    { OPCODE_PK4B,   "PK4B",  1 },
    { OPCODE_PK4UB,  "PK4UB", 1 },
    { OPCODE_POW,    "POW",   2 },
+   { OPCODE_POPA,   "POPA",  0 },
    { OPCODE_PRINT,  "PRINT", 1 },
+   { OPCODE_PUSHA,  "PUSHA", 0 },
    { OPCODE_RCC,    "RCC",   1 },
    { OPCODE_RCP,    "RCP",   1 },
+   { OPCODE_RET,    "RET",   1 },
    { OPCODE_RFL,    "RFL",   1 },
    { OPCODE_RSQ,    "RSQ",   1 },
    { OPCODE_SCS,    "SCS",   1 },
@@ -1022,12 +1030,14 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = {
    { OPCODE_SLE,    "SLE",   2 },
    { OPCODE_SLT,    "SLT",   2 },
    { OPCODE_SNE,    "SNE",   2 },
+   { OPCODE_SSG,    "SSG",   1 },
    { OPCODE_STR,    "STR",   0 },
    { OPCODE_SUB,    "SUB",   2 },
    { OPCODE_SWZ,    "SWZ",   1 },
    { OPCODE_TEX,    "TEX",   1 },
    { OPCODE_TXB,    "TXB",   1 },
    { OPCODE_TXD,    "TXD",   3 },
+   { OPCODE_TXL,    "TXL",   1 },
    { OPCODE_TXP,    "TXP",   1 },
    { OPCODE_TXP_NV, "TXP",   1 },
    { OPCODE_UP2H,   "UP2H",  1 },
diff --git a/src/mesa/shader/program_instruction.h b/src/mesa/shader/program_instruction.h
index 07a22145fa..8277c5ced9 100644
--- a/src/mesa/shader/program_instruction.h
+++ b/src/mesa/shader/program_instruction.h
@@ -70,17 +70,22 @@
  */
                      /* ARB_vp   ARB_fp   NV_vp   NV_fp */
 enum prog_opcode {   /*---------------------------------*/
-   OPCODE_ABS,       /*            X       1.1          */
+   OPCODE_ABS,       /*   X        X       1.1          */
    OPCODE_ADD,       /*   X        X       X       X    */
+   OPCODE_ARA,       /*                    2            */
    OPCODE_ARL,       /*   X                X            */
+   OPCODE_ARL_NV,    /*                    2            */
+   OPCODE_ARR,       /*                    2            */
+   OPCODE_BRA,       /*                    2            */
+   OPCODE_CAL,       /*                    2       2    */
    OPCODE_CMP,       /*            X                    */
-   OPCODE_COS,       /*   X                2            */
+   OPCODE_COS,       /*            X       2       X    */
    OPCODE_DDX,       /*                            X    */
    OPCODE_DDY,       /*                            X    */
    OPCODE_DP3,       /*   X        X       X       X    */
    OPCODE_DP4,       /*   X        X       X       X    */
    OPCODE_DPH,       /*   X        X       1.1          */
-   OPCODE_DST,       /*   X        X       X            */
+   OPCODE_DST,       /*   X        X       X       X    */
    OPCODE_END,       /*   X        X       X       X    */
    OPCODE_EX2,       /*   X        X       2       X    */
    OPCODE_EXP,       /*   X                X            */
@@ -90,7 +95,7 @@ enum prog_opcode {   /*---------------------------------*/
    OPCODE_KIL_NV,    /*                            X    */
    OPCODE_LG2,       /*   X        X       2       X    */
    OPCODE_LIT,       /*   X        X       X       X    */
-   OPCODE_LOG,       /*   X                X       X    */
+   OPCODE_LOG,       /*   X                X            */
    OPCODE_LRP,       /*            X               X    */
    OPCODE_MAD,       /*   X        X       X       X    */
    OPCODE_MAX,       /*   X        X       X       X    */
@@ -102,9 +107,12 @@ enum prog_opcode {   /*---------------------------------*/
    OPCODE_PK4B,      /*                            X    */
    OPCODE_PK4UB,     /*                            X    */
    OPCODE_POW,       /*   X        X               X    */
+   OPCODE_POPA,      /*                    3            */
    OPCODE_PRINT,     /*                    X       X    */
+   OPCODE_PUSHA,     /*                    3            */
    OPCODE_RCC,       /*                    1.1          */
    OPCODE_RCP,       /*   X        X       X       X    */
+   OPCODE_RET,       /*                    2       2    */
    OPCODE_RFL,       /*            X               X    */
    OPCODE_RSQ,       /*   X        X       X       X    */
    OPCODE_SCS,       /*            X                    */
@@ -116,48 +124,22 @@ enum prog_opcode {   /*---------------------------------*/
    OPCODE_SLE,       /*                    2       X    */
    OPCODE_SLT,       /*   X        X       X       X    */
    OPCODE_SNE,       /*                    2       X    */
-   OPCODE_STR,       /*            X       2       X    */
+   OPCODE_SSG,       /*                    2            */
+   OPCODE_STR,       /*                    2       X    */
    OPCODE_SUB,       /*   X        X       1.1     X    */
    OPCODE_SWZ,       /*   X        X                    */
-   OPCODE_TEX,       /*            X               X    */
-   OPCODE_TXB,       /*            X                    */
-   OPCODE_TXD,       /*            X               X    */
+   OPCODE_TEX,       /*            X       3       X    */
+   OPCODE_TXB,       /*            X       3            */
+   OPCODE_TXD,       /*                            X    */
+   OPCODE_TXL,       /*                    3       2    */
    OPCODE_TXP,       /*            X                    */
-   OPCODE_TXP_NV,    /*                            X    */
+   OPCODE_TXP_NV,    /*                    3       X    */
    OPCODE_UP2H,      /*                            X    */
    OPCODE_UP2US,     /*                            X    */
    OPCODE_UP4B,      /*                            X    */
    OPCODE_UP4UB,     /*                            X    */
    OPCODE_X2D,       /*                            X    */
    OPCODE_XPD,       /*   X        X                    */
-#if 0
-   OPCODE_ARA,		/* NV_vertex_program2 */
-   OPCODE_ARL_NV,		/* NV_vertex_program2 */
-   OPCODE_ARR,		/* NV_vertex_program2 */
-
-   OPCODE_SEQ,		/* NV_vertex_program2 */
-   OPCODE_SFL,		/* NV_vertex_program2 */
-   OPCODE_SGT,		/* NV_vertex_program2 */
-   OPCODE_SLE,		/* NV_vertex_program2 */
-   OPCODE_SNE,		/* NV_vertex_program2 */
-   OPCODE_STR,		/* NV_vertex_program2 */
-
-   OPCODE_SSG,		/* NV_vertex_program2 */
-   OPCODE_COS,		/* NV_vertex_program2 */
-   OPCODE_SIN,		/* NV_vertex_program2 */
-
-   OPCODE_BRA,		/* NV_vertex_program2 */
-   OPCODE_CAL,		/* NV_vertex_program2 */
-   OPCODE_RET,		/* NV_vertex_program2 */
-
-   OPCODE_PUSHA,		/* NV_vertex_program3 */
-   OPCODE_POPA,		/* NV_vertex_program3 */
-
-   OPCODE_TEX,		/* NV_vertex_program3 */
-   OPCODE_TXB,		/* NV_vertex_program3 */
-   OPCODE_TXL,		/* NV_vertex_program3 */
-   OPCODE_TXP,		/* NV_vertex_program3 */
-#endif
    MAX_OPCODE
 };
 
diff --git a/src/mesa/tnl/t_vb_arbprogram.c b/src/mesa/tnl/t_vb_arbprogram.c
index 78742759a5..27ff50932c 100644
--- a/src/mesa/tnl/t_vb_arbprogram.c
+++ b/src/mesa/tnl/t_vb_arbprogram.c
@@ -637,10 +637,19 @@ _tnl_disassem_vba_insn( union instruction op )
    case OPCODE_XPD:
       print_ALU(op);
       break;
+   case OPCODE_ARA:
    case OPCODE_ARL:
+   case OPCODE_ARL_NV:
+   case OPCODE_ARR:
+   case OPCODE_BRA:
+   case OPCODE_CAL:
    case OPCODE_END:
    case OPCODE_MAD:
+   case OPCODE_POPA:
+   case OPCODE_PUSHA:
    case OPCODE_RCC:
+   case OPCODE_RET:
+   case OPCODE_SSG:
    case OPCODE_SWZ:
       print_NOP(op);
       break;
@@ -663,7 +672,12 @@ static void (* const opcode_func[MAX_OPCODE+3])(struct arb_vp_machine *, union i
 {
    do_ABS,
    do_ADD,
+   do_NOP,/*ARA*/
    do_NOP,/*ARL*/
+   do_NOP,/*ARL_NV*/
+   do_NOP,/*ARR*/
+   do_NOP,/*BRA*/
+   do_NOP,/*CAL*/
    do_NOP,/*CMP*/
    do_NOP,/*COS*/
    do_NOP,/*DDX*/
@@ -693,9 +707,12 @@ static void (* const opcode_func[MAX_OPCODE+3])(struct arb_vp_machine *, union i
    do_NOP,/*PK4B*/
    do_NOP,/*PK4UB*/
    do_POW,
+   do_NOP,/*POPA*/
    do_PRT,
+   do_NOP,/*PUSHA*/
    do_NOP,/*RCC*/
    do_RCP,/*RCP*/
+   do_NOP,/*RET*/
    do_NOP,/*RFL*/
    do_RSQ,
    do_NOP,/*SCS*/
@@ -707,12 +724,14 @@ static void (* const opcode_func[MAX_OPCODE+3])(struct arb_vp_machine *, union i
    do_NOP,/*SLE*/
    do_SLT,
    do_NOP,/*SNE*/
+   do_NOP,/*SSG*/
    do_NOP,/*STR*/
    do_SUB,
    do_RSW,/*SWZ*/
    do_NOP,/*TEX*/
    do_NOP,/*TXB*/
    do_NOP,/*TXD*/
+   do_NOP,/*TXL*/
    do_NOP,/*TXP*/
    do_NOP,/*TXP_NV*/
    do_NOP,/*UP2H*/
@@ -935,7 +954,7 @@ static void cvp_emit_inst( struct compilation *cp,
    struct reg reg[3];
    GLuint result, nr_args, i;
 
-   assert(sizeof(*op) == sizeof(GLuint));
+   assert(sizeof(*op) == sizeof(long long));
 
    /* Need to handle SWZ, ARL specially.
     */
diff --git a/src/mesa/tnl/t_vb_arbprogram.h b/src/mesa/tnl/t_vb_arbprogram.h
index 93692c92cd..a3cf1d8ca1 100644
--- a/src/mesa/tnl/t_vb_arbprogram.h
+++ b/src/mesa/tnl/t_vb_arbprogram.h
@@ -71,7 +71,7 @@
 #define REG_INVALID ~0
 
 /* ARB_vp instructions are broken down into one or more of the
- * following micro-instructions, each representable in a 32 bit packed
+ * following micro-instructions, each representable in a 64 bit packed
  * structure.
  */
 struct reg {
@@ -82,17 +82,18 @@ struct reg {
 
 union instruction {
    struct {
-      GLuint opcode:6;
+      GLuint opcode:7;
       GLuint dst:5;
       GLuint file0:2;
       GLuint idx0:7;
       GLuint file1:2;
       GLuint idx1:7;
-      GLuint pad:3;
+      GLuint pad:2;
+      GLuint pad2;
    } alu;
 
    struct {
-      GLuint opcode:6;
+      GLuint opcode:7;
       GLuint dst:5;
       GLuint file0:2;
       GLuint idx0:7;
@@ -101,15 +102,16 @@ union instruction {
    } rsw;
 
    struct {
-      GLuint opcode:6;
+      GLuint opcode:7;
       GLuint dst:5;
       GLuint file:2;
       GLuint idx:7;
       GLuint mask:4;
-      GLuint pad:1;
+      GLuint pad:7;
+      GLuint pad2;
    } msk;
 
-   GLuint dword;
+   long long dword;
 };