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authorEric Anholt <eric@anholt.net>2009-08-18 18:48:54 -0700
committerEric Anholt <eric@anholt.net>2009-09-04 14:12:37 -0700
commita9504edee344936ef496341174d4c2d76ee0c44d (patch)
tree8faaf3a7bcaa9d852eb96801cfa0ea5214690003 /src/mesa
parent945d34e88ab7413299227fea56acc746010bb2e9 (diff)
intel: Align cubemap texture height to its padding requirements.
(cherry picked from commit a70e1315846cd5e8d6f2b622821ff8262fe7179d) (cherry picked from commit 29e51c3872531366570d032147abad50f8a3c1af)
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 51a617fcb4..3ab27c26ef 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -119,6 +119,16 @@ GLboolean brw_miptree_layout( struct intel_context *intel, struct intel_mipmap_t
}
}
+ /* The 965's sampler lays cachelines out according to how accesses
+ * in the texture surfaces run, so they may be "vertical" through
+ * memory. As a result, the docs say in Surface Padding Requirements:
+ * Sampling Engine Surfaces that two extra rows of padding are required.
+ * We don't know of similar requirements for pre-965, but given that
+ * those docs are silent on padding requirements in general, let's play
+ * it safe.
+ */
+ if (mt->target == GL_TEXTURE_CUBE_MAP)
+ mt->total_height += 2;
break;
}