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authorKrzysztof Czurylo <krzysztof.czurylo@intel.com>2008-07-30 10:19:08 -0700
committerIan Romanick <ian.d.romanick@intel.com>2008-08-21 15:01:59 -0700
commitbe30fddc7c6d0a75cf0777cf24591c3a6439e2c6 (patch)
treec834727c6a20804dc4c599fa3ba42f301655d9fa /src/mesa
parent1a244cd9e29e0163a3d68cc30cc6f4a81a9ea96d (diff)
965: Fix color clamping issues
Patch is correctly applied this time.
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs_emit.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index ad414f42cc..8759826e83 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1165,6 +1165,27 @@ void brw_vs_emit(struct brw_vs_compile *c )
brw_MOV(p, get_dst(c, inst->DstReg), dst);
}
+ /* Result color clamping.
+ *
+ * When destination register is an output register and
+ * it's primary/secondary front/back color, we have to clamp
+ * the result to [0,1]. This is done by enabling the
+ * saturation bit for the last instruction.
+ *
+ * We don't use brw_set_saturate() as it modifies
+ * p->current->header.saturate, which affects all the subsequent
+ * instructions. Instead, we directly modify the header
+ * of the last (already stored) instruction.
+ */
+ if (inst->DstReg.File == PROGRAM_OUTPUT) {
+ if ((inst->DstReg.Index == VERT_RESULT_COL0)
+ || (inst->DstReg.Index == VERT_RESULT_COL1)
+ || (inst->DstReg.Index == VERT_RESULT_BFC0)
+ || (inst->DstReg.Index == VERT_RESULT_BFC1)) {
+ p->store[p->nr_insn-1].header.saturate = 1;
+ }
+ }
+
release_tmps(c);
}