diff options
| author | Alan Hourihane <alanh@tungstengraphics.com> | 2003-12-10 19:12:49 +0000 |
|---|---|---|
| committer | Alan Hourihane <alanh@tungstengraphics.com> | 2003-12-10 19:12:49 +0000 |
| commit | 2ed479784859e01441eeaffc67e916aa6b863def (patch) | |
| tree | bdfbfd43c310eeeea064a824d16dc0d9022b5f18 /src | |
| parent | 28442852978e8ca0bcc5fda6393fc7b94fcf2bbf (diff) | |
fix from DRI trunk
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_sanity.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c index 3bc15bdcb4..451c73cf25 100644 --- a/src/mesa/drivers/dri/radeon/radeon_sanity.c +++ b/src/mesa/drivers/dri/radeon/radeon_sanity.c @@ -137,7 +137,7 @@ static struct { { 0, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, - { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" }, + { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, }; struct reg_names { @@ -178,22 +178,22 @@ static struct reg_names reg_names[] = { { RADEON_PP_TXFILTER_2, "RADEON_PP_TXFILTER_2" }, { RADEON_PP_TXFORMAT_0, "RADEON_PP_TXFORMAT_0" }, { RADEON_PP_TXFORMAT_1, "RADEON_PP_TXFORMAT_1" }, - { RADEON_PP_TXFORMAT_2, "RADEON_PP_TXFORMAT_3" }, + { RADEON_PP_TXFORMAT_2, "RADEON_PP_TXFORMAT_2" }, { RADEON_PP_TXOFFSET_0, "RADEON_PP_TXOFFSET_0" }, { RADEON_PP_TXOFFSET_1, "RADEON_PP_TXOFFSET_1" }, - { RADEON_PP_TXOFFSET_2, "RADEON_PP_TXOFFSET_3" }, + { RADEON_PP_TXOFFSET_2, "RADEON_PP_TXOFFSET_2" }, { RADEON_PP_TXCBLEND_0, "RADEON_PP_TXCBLEND_0" }, { RADEON_PP_TXCBLEND_1, "RADEON_PP_TXCBLEND_1" }, - { RADEON_PP_TXCBLEND_2, "RADEON_PP_TXCBLEND_3" }, + { RADEON_PP_TXCBLEND_2, "RADEON_PP_TXCBLEND_2" }, { RADEON_PP_TXABLEND_0, "RADEON_PP_TXABLEND_0" }, { RADEON_PP_TXABLEND_1, "RADEON_PP_TXABLEND_1" }, - { RADEON_PP_TXABLEND_2, "RADEON_PP_TXABLEND_3" }, + { RADEON_PP_TXABLEND_2, "RADEON_PP_TXABLEND_2" }, { RADEON_PP_TFACTOR_0, "RADEON_PP_TFACTOR_0" }, { RADEON_PP_TFACTOR_1, "RADEON_PP_TFACTOR_1" }, - { RADEON_PP_TFACTOR_2, "RADEON_PP_TFACTOR_3" }, + { RADEON_PP_TFACTOR_2, "RADEON_PP_TFACTOR_2" }, { RADEON_PP_BORDER_COLOR_0, "RADEON_PP_BORDER_COLOR_0" }, { RADEON_PP_BORDER_COLOR_1, "RADEON_PP_BORDER_COLOR_1" }, - { RADEON_PP_BORDER_COLOR_2, "RADEON_PP_BORDER_COLOR_3" }, + { RADEON_PP_BORDER_COLOR_2, "RADEON_PP_BORDER_COLOR_2" }, { RADEON_SE_ZBIAS_FACTOR, "RADEON_SE_ZBIAS_FACTOR" }, { RADEON_SE_ZBIAS_CONSTANT, "RADEON_SE_ZBIAS_CONSTANT" }, { RADEON_SE_TCL_OUTPUT_VTX_FMT, "RADEON_SE_TCL_OUTPUT_VTXFMT" }, |