diff options
| author | Keith Whitwell <keithw@vmware.com> | 2010-11-03 11:15:43 +0000 |
|---|---|---|
| committer | Keith Whitwell <keithw@vmware.com> | 2010-11-03 11:16:04 +0000 |
| commit | 32bb65217ed048817d314062f2804c79f80d0ec7 (patch) | |
| tree | efb79f0c17e4b60ceb00a540066951f783faa2f1 /src | |
| parent | d6b6a0bc170bd61abbbe9cb6ba777c7192dbd018 (diff) | |
evergreeng: set hardware pixelcenters according to gl_rasterization_rules
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/evergreend.h | 3 |
2 files changed, 8 insertions, 1 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 7dd261d7e2..4725b5e75e 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -291,7 +291,11 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx, r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL); - r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 0x00000005, 0xFFFFFFFF, NULL); + + r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, + S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules), + 0xFFFFFFFF, NULL); + r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL); return rstate; } diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h index 7e7bd01291..a337916c09 100644 --- a/src/gallium/drivers/r600/evergreend.h +++ b/src/gallium/drivers/r600/evergreend.h @@ -1690,6 +1690,9 @@ #define R_028C00_PA_SC_LINE_CNTL 0x00028C00 #define R_028C04_PA_SC_AA_CONFIG 0x00028C04 #define R_028C08_PA_SU_VTX_CNTL 0x00028C08 +#define S_028C08_PIX_CENTER_HALF(x) (((x) & 0x1) << 0) +#define G_028C08_PIX_CENTER_HALF(x) (((x) >> 0) & 0x1) +#define C_028C08_PIX_CENTER_HALF 0xFFFFFFFE #define R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x00028C0C #define R_028C10_PA_CL_GB_VERT_DISC_ADJ 0x00028C10 #define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ 0x00028C14 |