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authorEric Anholt <eric@anholt.net>2008-07-02 10:21:44 -0700
committerEric Anholt <eric@anholt.net>2008-07-02 10:21:44 -0700
commit4b3ed4d2d16811a624857519e95303017f4160b5 (patch)
treefabe8a116da19f6d4fd636f38f9dafdfcee24465 /src
parent19f585a3cf65887e249d630fe43e83e7e7618dfa (diff)
intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.
Apparently in Y mode we get bit 6 ^ bit 9. The reflect demo in 'd' mode now displays correctly.
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/intel/intel_span.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 6138b262f4..7b079afa73 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -183,6 +183,16 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
(x_tile_off & 0xf);
+
+ switch (intel->tiling_swizzle_mode) {
+ case 0:
+ break;
+ case 1:
+ tile_off ^= (tile_off >> 3) & 64;
+ break;
+ case 2:
+ break;
+ }
tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
return buf + tile_base + tile_off;