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authorAlex Deucher <alex@botch2.com>2008-05-28 10:11:14 +1000
committerDave Airlie <airlied@redhat.com>2008-05-28 10:11:14 +1000
commit867f5aac5361eda657491a98feca33c91eae3218 (patch)
tree9bf23aecb4027fe48e8b65083953fadbe545e983 /src
parent5552500cdfc4b97f5c824f6af1f8213c785693f9 (diff)
R3/4/5xx: update to use drm get_param for num gb pipes
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/r300/r300_state.c31
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_screen.c37
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_screen.h2
3 files changed, 42 insertions, 28 deletions
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index c0896acc23..6f1f4aac74 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -2201,36 +2201,25 @@ static void r300ResetHwState(r300ContextPtr r300)
r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_0] = 0x66666666;
r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_1] = 0x06666666;
- /* num pipes needs to be read back from the GB_PIPE_SELECT register
- * on r4xx/r5xx/rs4xx/rs6xx
- * should move this to the drm
- */
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] =
R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16 /*| R300_GB_SUBPIXEL_1_16*/;
- switch (r300->radeon.radeonScreen->chip_family) {
- case CHIP_FAMILY_R300:
- case CHIP_FAMILY_R350:
+ switch (r300->radeon.radeonScreen->num_gb_pipes) {
+ case 1:
+ default:
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_PIPE_COUNT_R300;
+ R300_GB_TILE_PIPE_COUNT_RV300;
break;
- case CHIP_FAMILY_RV350:
- case CHIP_FAMILY_RV515:
- case CHIP_FAMILY_RV530:
- case CHIP_FAMILY_RV410:
+ case 2:
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_PIPE_COUNT_RV300;
+ R300_GB_TILE_PIPE_COUNT_R300;
break;
- case CHIP_FAMILY_R420:
- case CHIP_FAMILY_R520:
- case CHIP_FAMILY_R580:
- case CHIP_FAMILY_RV560:
- case CHIP_FAMILY_RV570:
+ case 3:
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_PIPE_COUNT_R420;
+ R300_GB_TILE_PIPE_COUNT_R420_3P;
break;
- default:
+ case 4:
r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |=
- R300_GB_TILE_DISABLE; /* TODO: This disables tiling totally. I guess it happened accidentially. */
+ R300_GB_TILE_PIPE_COUNT_R420;
break;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index d840e22742..c962d23da1 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -649,15 +649,8 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
- /* RV410 SE chips have half the pipes of regular RV410
- * Need to get num pipes form the GB_PIPE_SELECT register
- */
case PCI_CHIP_RV410_5E4C:
case PCI_CHIP_RV410_5E4F:
- screen->chip_family = CHIP_FAMILY_RV380;
- screen->chip_flags = RADEON_CHIPSET_TCL;
- break;
-
case PCI_CHIP_RV410_564A:
case PCI_CHIP_RV410_564B:
case PCI_CHIP_RV410_564F:
@@ -854,6 +847,36 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->fbLocation = (temp & 0xffff) << 16;
}
+ if (screen->chip_family >= CHIP_FAMILY_RV515) {
+ ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
+ &temp);
+ if (ret) {
+ fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
+ switch (screen->chip_family) {
+ case CHIP_FAMILY_R300:
+ case CHIP_FAMILY_R350:
+ screen->num_gb_pipes = 2;
+ break;
+ case CHIP_FAMILY_R420:
+ case CHIP_FAMILY_R520:
+ case CHIP_FAMILY_R580:
+ case CHIP_FAMILY_RV560:
+ case CHIP_FAMILY_RV570:
+ screen->num_gb_pipes = 4;
+ break;
+ case CHIP_FAMILY_RV350:
+ case CHIP_FAMILY_RV515:
+ case CHIP_FAMILY_RV530:
+ case CHIP_FAMILY_RV410:
+ default:
+ screen->num_gb_pipes = 1;
+ break;
+ }
+ } else {
+ screen->num_gb_pipes = temp;
+ }
+ }
+
if ( sPriv->drm_version.minor >= 10 ) {
drm_radeon_setparam_t sp;
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 184b0d225e..ab859d55bd 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -105,6 +105,8 @@ typedef struct {
driOptionCache optionCache;
const __DRIextension *extensions[8];
+
+ int num_gb_pipes;
} radeonScreenRec, *radeonScreenPtr;
#define IS_R100_CLASS(screen) \