r300: attempt at trivial/clear on r5xx

3 files changed, 87 insertions, 25 deletions

diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h
index 5686e5a6e9..d15887fb1c 100644
--- a/src/gallium/drivers/r300/r300_cs.h
+++ b/src/gallium/drivers/r300/r300_cs.h
@@ -85,7 +85,7 @@ static uint32_t pack_float_32(float f)
 } while (0)
 
 #define OUT_CS_REG(register, value) do { \
-    debug_printf("r300: writing 0x%x to register 0x%x\n", value, register); \
+    debug_printf("r300: writing 0x%08X to register 0x%04X\n", value, register); \
     OUT_CS(CP_PACKET0(register, 0)); \
     OUT_CS(value); \
 } while (0)
@@ -93,7 +93,7 @@ static uint32_t pack_float_32(float f)
 /* Note: This expects count to be the number of registers,
  * not the actual packet0 count! */
 #define OUT_CS_REG_SEQ(register, count) do { \
-    debug_printf("r300: writing register sequence 0x%x\n", register); \
+    debug_printf("r300: writing register sequence of %d to 0x%04X\n", count, register); \
     OUT_CS(CP_PACKET0(register, ((count) - 1))); \
 } while (0)
 
diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h
index c1d5009b86..9281e6656f 100644
--- a/src/gallium/drivers/r300/r300_reg.h
+++ b/src/gallium/drivers/r300/r300_reg.h
@@ -1669,7 +1669,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #	define R300_TEX_INST_MASK               (7 << 15)
 
 /* Output format from the unfied shader */
-#define R300_US_OUT_FMT                     0x46A4
+#define R300_US_OUT_FMT_0                   0x46A4
 #	define R300_US_OUT_FMT_C4_8         (0 << 0)
 #	define R300_US_OUT_FMT_C4_10        (1 << 0)
 #	define R300_US_OUT_FMT_C4_10_GAMMA  (2 << 0)
@@ -1691,7 +1691,24 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #	define R300_US_OUT_FMT_C4_16_FP     (18 << 0)
 #	define R300_US_OUT_FMT_C_32_FP      (19 << 0)
 #	define R300_US_OUT_FMT_C2_32_FP     (20 << 0)
-#	define R300_US_OUT_FMT_C4_32_FP     (20 << 0)
+#	define R300_US_OUT_FMT_C4_32_FP     (21 << 0)
+#   define R300_C0_SEL_A				(0 << 8)
+#   define R300_C0_SEL_R				(1 << 8)
+#   define R300_C0_SEL_G				(2 << 8)
+#   define R300_C0_SEL_B				(3 << 8)
+#   define R300_C1_SEL_A				(0 << 10)
+#   define R300_C1_SEL_R				(1 << 10)
+#   define R300_C1_SEL_G				(2 << 10)
+#   define R300_C1_SEL_B				(3 << 10)
+#   define R300_C2_SEL_A				(0 << 12)
+#   define R300_C2_SEL_R				(1 << 12)
+#   define R300_C2_SEL_G				(2 << 12)
+#   define R300_C2_SEL_B				(3 << 12)
+#   define R300_C3_SEL_A				(0 << 14)
+#   define R300_C3_SEL_R				(1 << 14)
+#   define R300_C3_SEL_G				(2 << 14)
+#   define R300_C3_SEL_B				(3 << 14)
+#   define R300_OUT_SIGN(x)				(x << 16)
 
 /* ALU
  * The ALU instructions register blocks are enumerated according to the order
@@ -2987,7 +3004,7 @@ enum {
 #   define R500_US_CODE_RANGE_ADDR(x)			(x << 0)
 #   define R500_US_CODE_RANGE_SIZE(x)			(x << 16)
 #define R500_US_CONFIG					0x4600
-#   define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO		(1 << 1)
+#   define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO		(1 << 0)
 #define R500_US_FC_ADDR_0				0xa000
 #   define R500_FC_BOOL_ADDR(x)				(x << 0)
 #   define R500_FC_INT_ADDR(x)				(x << 8)
@@ -3031,7 +3048,7 @@ enum {
 #   define R500_FORMAT_TXHEIGHT(x)			(x << 11)
 #   define R500_FORMAT_TXDEPTH(x)			(x << 22)
 /* _0 through _3 */
-#define R500_US_OUT_FMT_0				0x46a4
+#define R500_US_OUT_FMT_0				0x46A4
 #   define R500_OUT_FMT_C4_8				(0 << 0)
 #   define R500_OUT_FMT_C4_10				(1 << 0)
 #   define R500_OUT_FMT_C4_10_GAMMA			(2 << 0)
diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c
index 48e0f54db9..f2d0183c98 100644
--- a/src/gallium/drivers/r300/r300_surface.c
+++ b/src/gallium/drivers/r300/r300_surface.c
@@ -42,7 +42,7 @@ static void r300_surface_fill(struct pipe_context* pipe,
         " dimensions %dx%d, color 0x%x\n",
         dest, x, y, w, h, color);
 
-BEGIN_CS(276);
+BEGIN_CS((caps->is_r500) ? 367 : 276);
 R300_PACIFY;
 OUT_CS_REG(R300_TX_INVALTAGS, 0x0);
 R300_PACIFY;
@@ -88,10 +88,9 @@ OUT_CS_REG(R300_GB_TILE_CONFIG, R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16);
 OUT_CS_REG(R300_GB_SELECT, R300_GB_FOG_SELECT_1_1_W);
 OUT_CS_REG(R300_GB_AA_CONFIG, 0x0);
 /* XXX point tex stuffing */
-OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4);
+OUT_CS_REG_SEQ(R300_GA_POINT_S0, 1);
 OUT_CS_32F(0.0);
-OUT_CS_32F(0.0);
-OUT_CS_32F(1.0);
+OUT_CS_REG_SEQ(R300_GA_POINT_S1, 1);
 OUT_CS_32F(1.0);
 OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 |
     (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT));
@@ -124,10 +123,11 @@ OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000);
 OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C);
 OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
 OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF);
-OUT_CS_REG(R300_US_OUT_FMT, 0x00001B00);
-OUT_CS_REG(0x46A8, 0x00001B0F);
-OUT_CS_REG(0x46AC, 0x00001B0F);
-OUT_CS_REG(0x46B0, 0x00001B0F);
+OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
+OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R);
+OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED);
+OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED);
+OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED);
 OUT_CS_REG(R300_US_W_FMT, 0x00000001);
 OUT_CS_REG(R300_US_CONFIG, 0x00000000);
 OUT_CS_REG(R300_US_PIXSIZE, 0x00000000);
@@ -152,14 +152,10 @@ OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
 r300_emit_blend_color_state(r300, &blend_color_clear_state);
 
 OUT_CS_REG(R300_RB3D_BLEND_COLOR, 0x00000000);
-OUT_CS_REG(0x4E54, 0x00000000); 
-OUT_CS_REG(0x4E58, 0x00000000);
-OUT_CS_REG(0x4E5C, 0x00000000);
-OUT_CS_REG(0x4E60, 0x00000000);
-OUT_CS_REG(0x4E64, 0x00000000);
-OUT_CS_REG(0x4E68, 0x00000000);
-OUT_CS_REG(0x4E6C, 0x00000000);
-OUT_CS_REG(0x4E70, 0x00000000);
+/* XXX: Oh the wonderful unknown */
+OUT_CS_REG_SEQ(0x4E54, 8);
+for (i = 0; i < 8; i++)
+    OUT_CS(0x00000000);
 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000);
 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF);
@@ -202,16 +198,65 @@ OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0001C000);
 OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) |
     ((w * 6) << R300_POINTSIZE_X_SHIFT));
 
-/* XXX RS block setup */
+/* XXX RS block and fp setup */
 if (caps->is_r500) {
-    OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
-    for (i = 0; i < 8; i++) {
+    OUT_CS_REG_SEQ(R500_RS_IP_0, 16);
+    for (i = 0; i < 16; i++) {
         /* I like the operator macros more than the shift macros... */
         OUT_CS((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
             (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
             (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
             (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
     }
+    R300_PACIFY;
+    OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
+    OUT_CS_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) |
+        R500_US_CODE_END_ADDR(1));
+    OUT_CS_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) |
+        R500_US_CODE_RANGE_SIZE(1));
+    OUT_CS_REG(R500_US_CODE_OFFSET, R500_US_CODE_OFFSET_ADDR(0));
+    R300_PACIFY;
+    OUT_CS_REG(R500_US_CMN_INST_0,
+               R500_INST_TYPE_OUT |
+               R500_INST_TEX_SEM_WAIT |
+               R500_INST_LAST |
+               R500_INST_RGB_OMASK_R |
+               R500_INST_RGB_OMASK_G |
+               R500_INST_RGB_OMASK_B |
+               R500_INST_ALPHA_OMASK |
+               R500_INST_RGB_CLAMP |
+               R500_INST_ALPHA_CLAMP);
+    OUT_CS_REG(R500_US_ALU_RGB_ADDR_0,
+               R500_RGB_ADDR0(0) |
+               R500_RGB_ADDR1(0) |
+               R500_RGB_ADDR1_CONST |
+               R500_RGB_ADDR2(0) |
+               R500_RGB_ADDR2_CONST);
+    OUT_CS_REG(R500_US_ALU_ALPHA_ADDR_0,
+               R500_ALPHA_ADDR0(0) |
+               R500_ALPHA_ADDR1(0) |
+               R500_ALPHA_ADDR1_CONST |
+               R500_ALPHA_ADDR2(0) |
+               R500_ALPHA_ADDR2_CONST);
+    OUT_CS_REG(R500_US_ALU_RGB_INST_0,
+               R500_ALU_RGB_SEL_A_SRC0 |
+               R500_ALU_RGB_R_SWIZ_A_R |
+               R500_ALU_RGB_G_SWIZ_A_G |
+               R500_ALU_RGB_B_SWIZ_A_B |
+               R500_ALU_RGB_SEL_B_SRC0 |
+               R500_ALU_RGB_R_SWIZ_B_R |
+               R500_ALU_RGB_B_SWIZ_B_G |
+               R500_ALU_RGB_G_SWIZ_B_B);
+    OUT_CS_REG(R500_US_ALU_ALPHA_INST_0,
+               R500_ALPHA_OP_CMP |
+               R500_ALPHA_SWIZ_A_A |
+               R500_ALPHA_SWIZ_B_A);
+    OUT_CS_REG(R500_US_ALU_RGBA_INST_0,
+               R500_ALU_RGBA_OP_CMP |
+               R500_ALU_RGBA_R_SWIZ_0 |
+               R500_ALU_RGBA_G_SWIZ_0 |
+               R500_ALU_RGBA_B_SWIZ_0 |
+               R500_ALU_RGBA_A_SWIZ_0);
 } else {
     OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
     for (i = 0; i < 8; i++) {