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-rw-r--r--common.py4
-rw-r--r--include/EGL/eglplatform.h3
-rw-r--r--src/gallium/auxiliary/util/u_simple_shaders.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw.c1
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw_upload.c2
-rw-r--r--src/mesa/drivers/dri/intel/intel_pixel_read.c13
-rw-r--r--src/mesa/drivers/dri/intel/intel_regions.c7
8 files changed, 28 insertions, 6 deletions
diff --git a/common.py b/common.py
index a687efc86f..ccb962981d 100644
--- a/common.py
+++ b/common.py
@@ -33,9 +33,9 @@ else:
default_machine = _platform.machine()
default_machine = _machine_map.get(default_machine, 'generic')
-if default_platform in ('linux', 'freebsd', 'darwin'):
+if default_platform in ('linux', 'freebsd'):
default_dri = 'yes'
-elif default_platform in ('winddk', 'windows', 'wince'):
+elif default_platform in ('winddk', 'windows', 'wince', 'darwin'):
default_dri = 'no'
else:
default_dri = 'no'
diff --git a/include/EGL/eglplatform.h b/include/EGL/eglplatform.h
index 83e89cd704..9e83b60003 100644
--- a/include/EGL/eglplatform.h
+++ b/include/EGL/eglplatform.h
@@ -69,7 +69,8 @@ typedef HWND NativeWindowType;
typedef HBITMAP NativePixmapType;
/** END Added for Windows **/
-#elif defined(__gnu_linux__) || defined(__FreeBSD__) || defined(__sun)
+#elif defined(__gnu_linux__) || defined(__FreeBSD__) || defined(__sun) || defined(__APPLE__)
+
/** BEGIN Added for X (Mesa) **/
#ifndef EGLAPI
diff --git a/src/gallium/auxiliary/util/u_simple_shaders.c b/src/gallium/auxiliary/util/u_simple_shaders.c
index 1b8da9b685..ab754296fa 100644
--- a/src/gallium/auxiliary/util/u_simple_shaders.c
+++ b/src/gallium/auxiliary/util/u_simple_shaders.c
@@ -131,8 +131,6 @@ util_make_fragment_tex_shader(struct pipe_context *pipe )
-
-
/**
* Make simple fragment color pass-through shader.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 26a64d6528..a5209ac41b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -390,6 +390,8 @@ struct brw_cached_batch_item {
struct brw_vertex_element {
const struct gl_client_array *glarray;
+ /** The corresponding Mesa vertex attribute */
+ gl_vert_attrib attrib;
/** Size of a complete element */
GLuint element_size;
/** Number of uploaded elements for this input. */
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 682094ff13..c53bd47bb5 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -187,6 +187,7 @@ static void brw_merge_inputs( struct brw_context *brw,
for (i = 0; i < VERT_ATTRIB_MAX; i++) {
brw->vb.inputs[i].glarray = arrays[i];
+ brw->vb.inputs[i].attrib = (gl_vert_attrib) i;
if (arrays[i]->StrideB != 0)
brw->vb.info.sizes[i/16] |= (brw->vb.inputs[i].glarray->Size - 1) <<
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index d49fb0fd95..4aa17fa02d 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -423,7 +423,7 @@ static void brw_prepare_vertices(struct brw_context *brw)
/* Queue the buffer object up to be uploaded in the next pass,
* when we've decided if we're doing interleaved or not.
*/
- if (i == 0) {
+ if (input->attrib == VERT_ATTRIB_POS) {
/* Position array not properly enabled:
*/
if (input->glarray->StrideB == 0) {
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c
index 8713463ace..30b06f281e 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c
@@ -261,6 +261,7 @@ do_blit_readpixels(GLcontext * ctx,
if (!intel_intersect_cliprects(&rect, &src_rect, &box[i]))
continue;
+<<<<<<< HEAD:src/mesa/drivers/dri/intel/intel_pixel_read.c
if (!intelEmitCopyBlit(intel,
src->cpp,
src->pitch, src->buffer, 0, src->tiling,
@@ -274,6 +275,18 @@ do_blit_readpixels(GLcontext * ctx,
UNLOCK_HARDWARE(intel);
return GL_FALSE;
}
+=======
+ intelEmitCopyBlit(intel,
+ src->cpp,
+ src->pitch, src->buffer, 0, src->tiling,
+ rowLength, dst_buffer, dst_offset, GL_FALSE,
+ rect.x1,
+ rect.y1,
+ rect.x1 - src_rect.x1,
+ rect.y2 - src_rect.y2,
+ rect.x2 - rect.x1, rect.y2 - rect.y1,
+ GL_COPY);
+>>>>>>> mesa_7_5_branch:src/mesa/drivers/dri/intel/intel_pixel_read.c
}
}
UNLOCK_HARDWARE(intel);
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 068a3f3379..a86c66a844 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -196,6 +196,13 @@ intel_region_alloc(struct intel_context *intel,
else
height = ALIGN(height, 2);
+ /* If we're untiled, we have to align to 2 rows high because the
+ * data port accesses 2x2 blocks even if the bottom row isn't to be
+ * rendered, so failure to align means we could walk off the end of the
+ * GTT and fault.
+ */
+ height = ALIGN(height, 2);
+
if (expect_accelerated_upload) {
buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
pitch * cpp * height, 64);